Skyworks Solutions, Inc.

Anadigics, Inc.

Mohsen Shokrani

Boris Gedzberg

Kezhou Xie

Oleh Krutko

Aditya K Gupta

Ronald L Michels

Ron Michels

A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.

Low cost metallization during fabrication of an integrated circuit (IC)

Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.

Structures and methods for fabricating vertically integrated HBT-FET device

Structures and methods for fabricating vertically integrated HBT/FET device

Growing community of inventors

Green Brook, NJ, United States of America

Mohsen Shokrani