Xilinx, Inc.

Other

Xilinix, Inc.

Mohsen Hossein Mardi

David M Mahoney

Gamal Refai-Ahmed

Suresh Ramalingam

Andy Widjaja

King Yon Lew

Elvin P Dang

Lik Huay Lim

Joseph M Juane

Jaspreet Singh Gandhi

Ivor G Barber

Myongseob Kim

Cinti Xiaohua Chen

Xin X Wu

Xiao-Yu Li

Hassan K Bazargan

Chih-Chung Wu

Tien-Yu Lee

Jae Cho

Sanjiv Stokes

Xuejing Che

Shih-Liang Liang

Stephen M Trimberger

Martin L Voogel

James Karp

Volker Aue

Hong Shi

Henley Liu

Cheang-Whang Chang

Siow Chek Tan

Brian Sadler

Eric D Hornchek

Owais E Malik

David Tan

Cosimo Cantatore

Joseph Macabante Juane

Micro devices having enhanced through heat transfer utilizing plungers extending from a heat spreader are provided. In one example, a micro device is provided that includes a plunger retaining block, a plurality of plungers, a mounting substrate and an integrated circuit (IC) die. The plunger retaining block includes a top surface and a bottom surface. The plurality of plungers extend from the bottom surface of the plunger retaining block with at least some of the plurality of plungers contacting the IC die. The IC die is disposed between the plunger retaining block and the mounting substrate, and coupled to the mounting substrate.

Micro device with adaptable thermal management device

A heat exchanger and an antenna assembly having the same are described herein that enable a compact antenna design with good thermal management. In one example, a heat exchanger is provided that includes tube-shaped body. A main cooling volume is formed between the top and bottom surfaces proximate to the outside wall. The main cooling volume has an inlet formed through the top surface and an outlet formed through the bottom surface. A return volume is formed adjacent the inside diameter wall and is circumscribed by the main cooling volume. The return volume has an outlet formed through the top surface and an inlet formed through the bottom surface. One or more exterior fins are coupled to an exterior side of the outside wall. A plurality of fins extend into the main cooling volume. A plurality of inner fins extend into a passage from the inside diameter wall.

Remote active cooling heat exchanger and antenna system with the same

Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

Method and apparatus of package enabled ESD protection

Examples described herein provide for testing of a test socket using multiple insertions to a contact resistance (CRES) test system. In an example, the test socket is placed in a first orientation on an interface board electrically connected to a test system. Using the test system and through the interface board, a first subset of probes of the test socket is tested while the test socket is in the first orientation on the interface board. The test socket is placed in a second orientation different from the first orientation on the interface board. Using the test system and through the interface board, a second subset of probes of the test socket is tested while the test socket is in the second orientation on the interface board. At least some probes of the second subset of probes are different from the first subset of probes.

Multiple insertion testing of test socket

A test system for testing a wafer for integrated circuit devices is described. The test system comprises a first plurality of test probes adapted to make electrical contacts to first corresponding contacts of a wafer tested by the test system; a second plurality of test probes adapted to make electrical contacts to second corresponding contacts on a perimeter region of a portion of the wafer tested by the test system; and a control circuit coupled to the first plurality of test probes and the second plurality of test probes; wherein the control circuit determines whether the second plurality of test probes has a proper contact with the wafer based upon signals received by the second plurality of test probes. A method of testing a wafer for an integrated circuit is also described.

Test system and method of testing a wafer for integrated circuit devices

A graphical tool for a design of a substrate of an integrated circuit device is described. The graphical tool comprises a processor configured to: display locations of probes for a first plurality of contact elements associated with the substrate; display locations of BGA contact elements associated with the substrate; identify interconnect elements between the first plurality of contact elements and the BGA contact elements; and display connections lines representing the identified interconnect elements. A method of designing a substrate of an integrated circuit device is also described.

Method of assigning contact elements associated with an integrated circuit device

A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.

Chip package assembly with power management integrated circuit and integrated circuit die

Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The lock ring housing is coupled to the rigid substrate. The circuit board is disposed between the lock ring housing and the rigid substrate. The lock ring is rotatable relative to the lock ring housing. Rotation of the lock ring is configured to move the lock ring in a direction perpendicular to the surface of the circuit board.

Probe head securing mechanism for probe assembly

Examples of the present disclosure generally relate to a probe head assembly having modular interposer and a test system having the same. In one example, a probe head assembly includes a rigid stiffener plate, a PIB substrate, a bracket, a plurality of interposers disposed in the bracket, a probe card board electrically coupled by a plurality of contact pins disposed through the interposers to the PIB substrate, and a probe card electrically coupled to the probe card board. The PIB substrate, the interposers and the probe card board are sandwiched between the stiffener plate and the probe card.

Probe head assembly

An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress includes a plurality of pusher pins. The plurality of pusher pins have tips extending from a bottom surface of the workpress. Each of the plurality of pusher pins is configured to apply an independent and discrete force to the chip package assembly disposed in the socket.

Integrated circuit package testing system

An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.

Chip package test system

Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

Testing system for lid-less integrated circuit packages

A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, an IC test system is provide that includes a robot, an input queuing station, an output queuing station, and a test station. The test station includes a first and second test interfaces. The first test interface is configurable to receive and communicatively connect with a first chip package assembly having one arrangement of solder ball connections. The second test interface is configurable to receive and communicatively connect with a second chip package assembly having a different arrangement of solder ball connections. The test station also includes a first test processor configured to test the chip package assembly connected through the first interface utilizing a predetermined first test routine and a second test processor configured to test the chip package assembly connected through the second interface utilizing a predetermined second test routine.

Versatile testing system

An electrically insulative pusher pin is disclosed. In one example, an electrically insulative pusher pin includes a first plunger member, a second plunger member, and a spring. The first plunger member has a first end and an exposed second end. The second plunger member has a first end and an exposed second end. The second plunger member is movable relative to the first plunger member, where the exposed second ends of the first and second plunger members defining a length of the pusher pin. The spring disposed between the first ends of the first and second plunger members and biases the exposed second end of the first plunger member away from the exposed second end of the second plunger member. An electrically insulative path is defined between the exposed second end of the first plunger member and the exposed second end of the second plunger member through the pusher pin.

Pusher pin having a non-electrically conductive portion

A chip package assembly testing system and method for testing a chip package assembly are provided herein. In one example, the testing system includes a robot disposed in an enclosure and having a range of motion operable to transfer a chip package assembly between any of a first queuing station, a second queuing station and a plurality of test stations. The system also includes an automatic identification and data capture (AIDC) device operable to read an identification tag affixed to a carrier disposed in the first and second queuing stations, and a controller configured to control placement of chip package assemblies by the robot in response information obtained from a carrier disposed in at least one of the first and second queuing stations, the predefined test routine of the test processor of the first test station, and the predefined test routine of the test processor of the second test station.

Growing community of inventors

Saratoga, CA, United States of America

Mohsen Hossein Mardi