Intel Corporation

Mohsen Alavi

Mark T Bohr

Vivek K De

Muhammad M Khellah

Dinesh Somasekhar

Fabrice Paillet

Stephen H Tang

Yibin Ye

Ali Keshavarzi

Tahir Ghani

Ebrahim Andideh

Scott E Thompson

Tanay Karnik

Martin Spence Denham

Gilroy J Vandentop

Rachael Jade Parker

Kaizad Rumy Mistry

Sunit Tyagi

Wenliang Chen

Payman Aminzadeh

Patrick John Ott

Robert A Gasser

Min-Chun Tsai

Paul Gregory Slankard

A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

Dual gate oxide one time programmable (OTP) antifuse cell

A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

Apparatus and method for programming a memory array

Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

Crosspoint memory array utilizing one time programmable antifuse cells

Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.

OTP antifuse cell and cell array

A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.

Overvoltage detection apparatus, method, and system

A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.

Static, low-voltage fuse-based cell with high-voltage programming

A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

Structure and process flow for fabrication of dual gate floating body integrated MOS transistors

A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer sited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

A fusible link device disposed on a semiconductor substrate for providing discretionary changes in resistance. The fusible link device of the invention includes a polysilicon layer having a first resistance. A silicide layer formed on the polysilicon layer has a second, lower resistance and includes a fuse region having a first notched region narrower than the center of the fuse region, a first contact region electrically coupled to one end of the fuse region and a second contact region electrically coupled to an opposite end of the fuse region. The silicide layer agglomerates to form an electrical discontinuity in the fuse region (usually in the notched region) in response to a current greater than or equal to a predetermined programming current flowing between the contact regions, such that the resistance of the fusible link device can be selectively increased.

Silicide agglomeration fuse device with notches to enhance programmability

A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the suicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.

Silicide agglomeration fuse device

A method and an apparatus for forming a transistor suitable for a high voltage circuit. In one embodiment, the transistor is formed without adding any steps to an existing state-of-the-art CMOS process. A well is implanted into a portion of a substrate such that the well has a higher doping concentration than the substrate. A first diffusion region is then implanted into the substrate such that at least a portion of the first diffusion is disposed within the well. In addition, a second diffusion is implanted into the substrate separated from the well such that the second diffusion region is disposed entirely outside the well. A channel region is disposed between the first and second regions and gate is disposed over the channel region to form the high voltage transistor. Since the second diffusion region is disposed entirely outside the well in the lower doped substrate, a higher junction breakdown voltage is realized. Furthermore, with the transistor layout described herein having at least a portion of the first diffusion region disposed within the well, adequate device isolation is also realized.

Transistor suitable for high voltage circuit

A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first unprogrammed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance

Silicide agglomeration device

A monitoring device to monitor process induced charge employing a single layer of polysilicon forming a floating gate. The device comprises two capacitors, one for charging and the other for discharging a floating gate of an n-channel transistor. Embodiments which permit the monitoring of positive charge, negative charge and both positive and negative charge are described. The device is reusable and lends itself to in-line monitoring as opposed to some prior art devices used for end-of-line monitoring.

Single poly devices for monitoring the level and polarity of process

A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.

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Portland, OR, United States of America

Mohsen Alavi