Acme Packet, Inc.

Acme Products, Inc.

Mohiuddin Mohammed Khan

Patrick John MeLampy

Robert F Penfield

Ephraim Webster Dobbins

Stephen Norton

Pietro Botticelli

Systems and methods for routing media packets between a plurality of processors and a digital signal processor (DSP) are disclosed. An exemplary device comprises: an egress processor; an ingress processor; conversion logic; and a DSP configured to transcode a payload in the packet. The ingress processor is configured to change a first layer-2 header of a received media packet to a second layer-2 header. The second layer-2 header includes a DSP address and an egress processor address. The first layer-2 header has a first format and the second layer-2 header having a second different format. The conversion logic is configured to change the second layer-2 header to a third layer-2 header, and to change the third layer-2 header to a fourth layer-2 header including the egress processor address in the first format. The third layer-2 header includes the egress processor address in the first format.

Method and system of routing media packets in a network device

Systems and methods for redundancy in a network device are disclosed. An exemplary network device comprises: a plurality of data forwarding elements (DFEs); and a redundant control plane. The redundant control plane comprises: an active control processor for configuring forwarding operation of each of the DFEs; an active layer-2 switch coupled to the active control processor and to each of the DFEs; a standby control processor; and a standby layer-2 switch coupled to the standby control processor and to each of the DFEs. The active control processor is programmed in a full-mesh so that the active control processor is in communication with each of the DFEs. The standby control processor is programmed in a full-mesh so that the standby control processor is in communication with each of the DFEs.

Method and system of providing redundancy in a network device

A system and method for providing statistics gathering within a packet network is disclosed. The system comprises a network processor, a traffic manager, a host processor, and a field programmable gate array. The network processor adds a header to received multimedia packets and the traffic manager measures and enforces multimedia flow rates. The host processor performs multimedia flow quality measurement services on a per flow basis, wherein the multimedia flow quality measurement services comprise maintaining current statistics for multimedia flows within the network processor including aggregate and minimum/maximum statistics for the multimedia flow. The field programmable gate array (FPGA) copies a received multimedia packet or a portion of the received multimedia packet, wherein the copy is utilized by the FPGA to perform statistics gathering via use of a latency engine, a lost packet calculation engine, a real-time transport control protocol packet jitter engine and a real-time transport protocol packet jitter engine.

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Lowell, MA, United States of America

Mohiuddin Mohammed Khan