Texas Instruments Corporation

Wipro Limited

Alliance Semiconductor Corporation

Avago Technologies International Sales Pte. Limited

Mohit Sharma

Pamela Kumar

Damodar Reddy Thummalapally

Tavare Dhanaraj B

Raghottam Mannopantar

Avinash Agarwal

Srinivas Adyapak

Cyril John Chemparathy

A system includes a frequency-locked loop (FLL) circuit, a sensor-hub circuit and a processor. The FLL circuit is used to generate a low-frequency clock. The sensor-hub circuit is coupled to a number of sensors and is configured to periodically poll the sensors during polling periods and to detect sensor activities. The processor is coupled to the sensor-hub circuit and can process sensor signals from one or more active sensors. The processor is off during polling periods and is turned on when a sensor activity is detected. The polling periods are based on the low-frequency clock generated by the FLL circuit.

Ultralow-power sensor hubs

A system and method for data cleansing are disclosed. The method includes receiving by a data classifier, a data corpus comprising one or more words. The method further includes grouping the one or more words into a plurality of pre-defined categories and determining an overlap ratio between each pair of the plurality of pre-defined categories based on a comparison between each of the plurality of pre-defined categories. A normalized overlap ratio is computed for each of the plurality of pre-defined categories based on a combination of each overlap ratio. At least one of the plurality of pre-defined categories is determined based on a comparison between each of the normalized overlap ratio and an ideal overlap ratio. Finally, one or more common words from the selected at least one of the plurality of pre-defined categories is removed based on a frequency of occurrence of the one or more common words.

System and method of data cleansing for improved data classification

This technology relates generally to data classification, and more particularly to system and method for classifying an input statement with respect to a small dataset. In one embodiment, a method is provided for classifying an input statement with respect to a small dataset. The method comprises receiving the input statement, extracting a plurality of input keywords from the input statement, computing a membership score for each of a plurality of category ontology trees based on the plurality of input keywords, and determining a classification of the input statement based on the membership score. The plurality of category ontology trees are derived from the small dataset and correspond to a plurality of classifications in the small dataset.

System and method for classifying data with respect to a small dataset

A high speed parser containing a content addressable memory (CAM) providing select values to multiplexers. The CAM is programmed to implement search rules which examine input data for specific semantics according to a protocol, and outputs the specific bit positions at which the corresponding desired data units are present. The outputs are provided to multiplexers to cause the desired data units to be selected on the corresponding output paths of the multiplexors.

High speed parser

A method is provided for prioritizing the entries in a database, where each entry is composed of multiple dimensions. Prioritization is required when there are multiple matches in the database. The number of matches can be the same as the number of entries in the database. To prioritize such a huge number of entries in a minimum number of clock cycles, a distributed prioritizer is implemented by partitioning stored binary data into half nibbles comprising of two bits of data each. Each half nibble is encoded into an expanded format allotting priority value to the stored encoded half nibbles. The stored encoded half nibbles are compared across a word array to determine an exact match.

Method for the prioritization of database entries

A multiplexer containing multiple cells sharing a common output line. The cells select one of multiple input bits. The output line is first charged to a first logical value (e.g., 0), and one of the cells drives the output line to a second logical value (1) if the corresponding input bit does not equal the first logical value. The remaining cells may not affect the output line. Due to such an implementation, the number of transistors may be reduced.

Multiplexer

A range check array structure for searching and comparing external data from an external search data key is disclosed. The structure has data storage means with at least one of an upper limit field, and a lower limit field, and one or more bit lines running therethrough for transmitting an input data word for comparison with the stored data word range. The input data word being compared with a respective stored data word to detect a match that is indicated along a match line by the check array structure. The check array structure further includes a range match detection means connected to the match line to determine the match or mismatch of the applied data stream with the stored data in each range check cell.

Growing community of inventors

Bengaluru, India

Mohit Sharma