Nxp Usa, Inc.

Mohit Satsangi

Ray Charles Marshall

Thomas Henry Luedeke

Prabhjot Singh

David W Todd

Loic Hureau

Tommi Jorma Mikael Jokinen

Andreas Bening

David Schuchmann

Alexandru Marginean

A system comprising a real time clock, RTC, and a processor configured to execute a secure application to provide a secure clock and configured to operate in a first low-power-mode and a first normal-mode, and a non-secure application configured to perform a clock modification procedure and configured to operate in a second low-power-mode and a second normal-mode, the system configured to perform a secure clock initialisation procedure comprising obtaining a record of a current time from the RTC based on a transition from the first low-power-mode to the first normal-mode, wherein the secure application is configured to perform a clock update procedure including updating the RTC with a secure record of the current time and wherein the system is further configured to prevent performing the clock modification procedure after the clock update procedure has been performed.

System including a secure application configured to perform a clock update procedure

Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.

Processing wakeup requests in a processing system having power management circuitry and a processing circuitry

A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

ID-based transaction routing for PCIe endpoint lending

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New Delhi, India

Mohit Satsangi