Intel Corporation

Other

University of Massachusetts

Mohit Mamodia

Dingying David Xu

Rahul N Manepalli

Leonel R Arana

Kyle Yazzie

Johanna M Swan

John Stephen Guzek

Nachiket R Raravikar

Ravi Kiran Nalla

Rajasekaran Swaminathan

Javier Soto Gonzalez

Pramod Malatkar

Edward Rudolph Prack

Xavier Francois Brun

Todd P Albertson

Drew W Delaney

Edward A Zarbock

David M Craig

Suresh V Pothukuchi

Joseph D Stanford

Chia-Pin Chiu

Jorge A Sanchez

Paul J Diglio

Kuang C Liu

Mark J Gallina

Arjun Krishnan

Vijay Wakharkar

Nirupama Chakrapani

Shankar Ganapathysubramanian

Shengquan Ou

Alan J Lesser

Naga Sivakumar Yagnamurthy

David Q Xu

Rajesh Kumar Neerukatti

Hualiang Shi

Wen Feng

Joseph Bautista

Naveen Kumar Singh

Michael Gregory Drake

Javier S Gonzalez

Shweta Agrawal

Hao Wu

Javier Solo Gonzalez

A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.

Probe pins with etched tips for electrical die test

An apparatus is provided which comprises: a substrate to couple with one or more integrated circuit die(s), an integrated circuit die coupled to the substrate, a metal component coupled to the substrate, wherein the metal component lacks a sealing coating, and a sacrificial metal conductively coupled with the metal component, wherein the sacrificial metal comprises a more anodic metal than the metal component. Other embodiments are also disclosed and claimed.

Package with cathodic protection for corrosion mitigation

Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.

Integrated circuit packages with patterned protective material

A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.

Thermal head with a thermal barrier for integrated circuit die processing

Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.

Stiffener tape for electronic assembly

Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.

Structures to mitigate contamination on a back side of a semiconductor substrate

An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a patterned die backside film (DBF) on a backside of a die, wherein the patterned DBF comprises an opening surrounding at least one through silicon via (TSV) pad disposed on the backside of the die.

Forming die backside coating structures with coreless packages

A coating for a microelectronic device comprises a polymer film () containing a filler material (). The polymer film has a thermal conductivity greater than 3 W/m&#xb7;K and a thickness () that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape () to form a treatment () that simplifies a manufacturing process for a microelectronic package () and may be used in order to manage a thermal profile of the microelectronic device.

Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die

A treatment for a microelectronic device comprises a dicing tape () and a polymer composite film () having a pigment or other colorant added thereto and, in some embodiments, a pre-cure glass transition temperature greater than 50&#xb0; Celsius. The film can comprise multiple layers, with one layer being tacky and the other layer non-tacky at a given temperature.

Treatment for a microelectronic device and method of resisting damage to a microelectronic device using same

Disclosed herein is a polymeric composition comprising a polymeric composition comprising a first crosslinked network; and a second crosslinked network; wherein the first crosslinked network is crosslinked at a first stress and/or a first strain and the second crosslinked network is crosslinked at a second stress and/or a second strain; where the first stress and/or the first strain is different from the second stress and/or the second strain either in magnitude or direction. Disclosed herein is a method comprising subjecting a polymeric mass to a first stress and/or a first strain level; crosslinking the polymeric mass to form a first crosslinked network; subjecting the polymeric mass to a second stress and/or a second strain level; and crosslinking the polymeric mass to form a second crosslinked network; where the first stress and/or the first strain level is different from the second stress and/or the second strain level.

Polymeric compositions, methods of manufacture thereof and articles comprising the same

Growing community of inventors

Chandler, AZ, United States of America

Mohit Mamodia