Applied Materials, Inc.

Other

Xilinx, Inc.

Jasper Design Automation, Inc.

Mohit Kumar Jain

Michael S Barnes

John Patrick Holland

Thorsten B Lill

Ajay Kumar

Dan Maydan

Jeffrey D Chinn

Ashok K Sinha

Alexander Miller Paterson

Chentsau Chris Ying

Diana Xiaobing Ma

Bryan Y Pu

Michael D Armacost

Chung-Wah Norris Ip

Hongqing Shan

Shekhar Bapat

Xiaoyi Chen

Valentin N Todorov

Stephen Yuen

Zhifeng Sui

Jeff Chinn

John Chao

Neil E Hanson

While performing functional verification on a circuit design, a verification tool allows a user to analyze the results of a previous functional analysis. The tool may also receive commands for a next verification analysis while performing a current analysis, and it may allow a user to abort a current analysis. Results from a completed analysis may be discarded or saved for viewing by a user while a next verification is performed on the circuit design. This allows a user to continue to debug and analyze the circuit design without having to wait until previous steps in the verification analysis are completed.

Interactive analysis and debugging of a circuit design during functional verification of the circuit design

Methods of testing a user design implemented in a programmable integrated circuit (IC). The programmable IC is programmed with a first test design that includes the user design and a first test circuit, and a first test pattern is run. The programmable IC is then programmed with a second test design that includes the user design and a second test circuit, and a second test pattern is run. If one of the test patterns fails and the other passes, the programmable IC passes the test sequence. Because one of the test patterns passed, the error in the other test pattern must have occurred in the test circuit, which is not necessary for the functioning of the user design in the programmable IC. Thus, the success of one test pattern shows that the flawed resource is not included in the portion of the programmable IC utilized for implementing the user design.

Methods of testing a user design in a programmable integrated circuit

A method of etching a magnetic material (e.g., nickel-iron alloy (NiFe), cobalt-iron alloy (CoFe), and the like) using a gas mixture comprising a hydrogen halide gas and a fluorocarbon-containing gas is disclosed. The method provides high etch selectivity for the magnetic materials over non-magnetic dielectric materials, such as aluminum oxide (AlO) and the like, as well as to photoresist.

Method of etching a magnetic material

A substrate processing method comprises providing a substratecomprising etch resistant materialin a process zone, such as an energized gas zone in a process chamber. The etch resistant materialmay comprise a resist materialover mask material. The process may further comprise removing the etch resistant material, such as the resist material, in the process zonebefore etching underlying layers.

Etching a substrate in a process zone

A substrate processing apparatus has a chamber having a substrate support, gas distributor, gas energizer, and gas exhaust port. A process monitor is provided to monitor features in a first region of the substrate and generate a corresponding first signal, and to monitor features in a second region of the substrate and generate a second signal. A chamber controller receives and evaluates the first and second signals, and operates the chamber in relation to the signals. For example, the chamber controller can select a process recipe depending upon the signal values. The chamber controller can also set a process parameter at a first level in a first processing sector and at a second level in a second processing sector. The apparatus provides a closed control loop to independently monitor and control processing of features at different regions of the substrate.

Monitoring dimensions of features at different locations in the processing of substrates

The present invention generally provides a method for processing a semiconductor substrate, wherein the method includes positioning a substrate in a processing chamber having at least a first and second coils positioned above the substrate and supplying a first electrical current to the first coil. The method further includes supplying a second current to the second coil and regulating a current ratio of electrical current supplied to the first and second coils with a power distribution network in communication with the first and second coils and a single power supply. The method may further include controlling plasma uniformity in a semiconductor processing chamber, wherein the control process includes positioning a first coil above the processing chamber, the first coil being concentrically positioned about a vertical axis of the processing chamber, and positioning a second coil above the processing chamber, the second coil being concentrically positioned about the vertical axis of the processing chamber and radially outward from the first coil. The control process may further include supplying electrical power to the first and second coils with a single power distribution network to selectively regulate a magnetic field intensity generated by the first and second coils above a workpiece in the processing chamber.

Method for controlling etch uniformity

The present invention provides a method for the simultaneous removal of an oxygen and/or nitrogen-containing dielectric antireflective coating (&ldquo;DARC&rdquo;) during plasma etching of an underlying layer in a film stack. According to the method of the invention, the film stack is etched using a plasma containing reactive fluorine species. The concentration of reactive fluorine species within the plasma is controlled based on one or more of the following factors: the oxygen content of the antireflective coating, the nitrogen content of the antireflective coating, the thickness of the antireflection coating layer, and the thickness of the underlying film stack layer. The disclosure of the invention provides preferred combinations of plasma source gases which provide for the simultaneous removal of an oxygen and/or nitrogen-containing DARC layer during etching of an underlying etch stack layer, where the underlying stack layer comprises a metal silicide, polysilicon, or a metal. Also provided herein is a formula for determining the total amount of DARC removed using a given etch process recipe, based on the etch selectivity of the particular process recipe

Method for in situ removal of a dielectric antireflective coating during a gate etch process

A method for processing a substrate disposed in a substrate processing chamber to modify the contour of a trench formed on the substrate. The substrate processing chamber is the type that has a coil and a plasma generation system including a source power system operatively coupled to the coil and a bias power system operatively coupled to the substrate process chamber. The method includes transferring the substrate into the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a first process gas consisting essentially of a sputtering agent by applying RF energy from the source power system to the coil. The plasma is biased toward the substrate by applying bias power to the substrate process chamber. Thereafter, the substrate is exposed to a plasma formed from a second process gas without applying bias power or applying minimal bias power to the substrate process chamber.

Method for rounding corners and removing damaged outer surfaces of a trench

Growing community of inventors

San Jose, CA, United States of America

Mohit Kumar Jain