International Business Machines Corporation

Mohit Karve

Brian William Thompto

George W Rohrbaugh, Iii

Naga P Gorti

Vivek Britto

Edmund Joseph Gieske

Bernard Charles Drerup

Guy L Guthrie

Balaram Sinharoy

Joel Abraham Silberman

Richard James Eickemeyer

Bryan J Lloyd

John Barry Griswell, Jr

Alper Buyuktosunoglu

Sanjeev Ghai

David A Campbell

Donald Ray Stence

Aaron Dingler

A core simulator includes one or more simulated processors, a trace-based traffic generator, and a simulated memory subsystem. Each simulated processor includes a core element and at least one lower-level cache excluded from the core element. The trace-based traffic generator includes a plurality of modeled caches that model the at least lower-level cache without modeling the core element. The trace-based traffic generator is configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic to be processed by the simulated memory subsystem. The simulated memory subsystem is shared between the at least one simulated processor and the trace-based traffic generator. The trace-based traffic generator performs a data exchange with the memory subsystem based on the at least one workload trace. The data exchange impacts a measured performance of the at least one simulated processor.

Processor core simulator including trace-based coherent cache driven memory traffic generator

An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.

Methods and systems for translating virtual addresses in a virtual memory based system

A method, programming product, and/or system for prefetching instructions includes an instruction prefetch table that has a plurality of entries, each entry for storing a first portion of an indirect branch instruction address and a target address, wherein the indirect branch instruction has multiple target addresses and the instruction prefetch table is accessed by an index obtained by hashing a second portion of bits of the indirect branch instruction address with an information vector of the indirect branch instruction. A further embodiment includes a first prefetch table for uni-target branch instructions and a second prefetch table for multi-target branch instructions. In operation it is determined whether a branch instruction hits in one of the multiple prefetch tables; a target address for the branch instruction is read from the respective prefetch table in which the branch instruction hit; and the branch instruction is prefetched to an instruction cache.

Multi-table instruction prefetch unit for microprocessor

A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.

Prefetch unit filter for microprocessor

A method, system, and computer program product for augmenting cache replacement operations are provided. The method identifies a set of cache lines within a first cache level of a multilevel cache. A first candidate cache line is identified based on a first replacement scheme of the first cache level. A second candidate cache line is identified based on the first replacement scheme of the first cache level. A replacement cache line is selected for replacement in the first cache level. The replacement cache line is selected from the first candidate cache line and the second candidate cache line and based on the first replacement scheme of the first cache level and a second replacement scheme of a second cache level. The method removes the replacement cache line from the first cache level.

Augmenting cache replacement operations

A processor may initialize a fetch of a first instruction. The processor may determine whether there is an icache miss for the first instruction. The processor may fetch the next instruction from a cache.

Miss-driven instruction prefetching

A Bloom filter is used to track contents of a cache. A system checks the Bloom filter before deciding whether to prefetch an address (by hashing the address and checking a value of the Bloom filter at an index based on the hash). This allows the system to utilize more aggressive prefetching schemes by reducing the risk of wasteful redundant prefetch operations.

Fast cache tracking to support aggressive prefetching

A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to generate a first prefetch request and a second prefetch request based on the demand access stream, to output the first prefetch request to a first translation lookaside buffer (TLB), and to output the second prefetch request to a second TLB that is different from the first TLB. The processor performs a first TLB lookup in the first TLB based on one of the demand access stream or the first prefetch request, and performs a second TLB lookup in the second TLB based on the second prefetch request.

Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers

Translating virtual addresses to second addresses by a memory controller local to one or more memory devices, wherein the memory controller is not local to a processor, a buffer for storing a plurality of Page Table Entries, or a Page Walk Cache for storing a plurality of page directory entries, the method including by the memory controller: receiving a page directory base and a plurality of memory offsets from the processor; reading a first level page directory entry using the page directory base and a first level memory offset; combining the second level offset and the first level page directory entry; reading a second level page directory entry using the first level page directory entry and the second level memory offset; sending to the processor the first level page directory entry or the second level page directory entry; and sending a page table entry to the processor.

Translating virtual addresses in a virtual memory based system

A computer-implemented method of performing a link stack based prefetch augmentation using a sequential prefetching includes observing a call instruction in a program being executed, and pushing a return address onto a link stack for processing the next instruction. A stream of instructions is prefetched starting from a cached line address of the next instruction and is stored in an instruction cache.

Link stack based instruction prefetch augmentation

A computer-implemented method to prefetch non-sequential instruction addresses (I/A) includes, determining, by a prefetch system, a first access attempt of a first I/A in a cache is a first miss, wherein the first I/A is included in a string of I/A's. The method further includes storing the first I/A in a linked miss-to-miss (LMTM) table. The method also includes determining a second access attempt of a second I/A in the cache is a second miss, wherein the second I/A is included in the string of I/A's. The method includes linking, in the LMTM table, the second miss to the first miss. The method also includes prefetching, in response to a third access attempt of the first I/A, the second I/A in the cache.

Linked miss-to-miss instruction prefetcher

Disclosed is a computer-implemented method to increase the efficiency of a prefetch system. The method includes receiving a system call including an instruction address. The method includes determining a confidence score. The method further includes creating an entry, including the instruction address, an associated data address, and the confidence score. The method includes determining the instruction address is not present in a history table, where the history table includes a plurality of entries. The method further includes determining, in response to adding the first entry to the history table, a second entry is evicted from the history table. The method includes entering the second entry into a filter table in response to determining the second confidence score is a moderate confidence score, where the moderate confidence score is any confidence score that is greater than a predefined low threshold and less than a predefined high threshold.

Prefetch filter table for storing moderately-confident entries evicted from a history table

In at least one embodiment, a processing unit includes a processor core and a vertical cache hierarchy including at least a store-through upper-level cache and a store-in lower-level cache. The upper-level cache includes a data array and an effective address (EA) directory. The processor core includes an execution unit, an address translation unit, and a prefetch unit configured to initiate allocation of a directory entry in the EA directory for a store target EA without prefetching a cache line of data into the corresponding data entry in the data array. The processor core caches in the directory entry an EA-to-RA address translation information for the store target EA, such that a subsequent demand store access that hits in the directory entry can avoid a performance penalty associated with address translation by the translation unit.

Prefetch store preallocation in an effective address-based cache directory

An information handling system, method, and processor that detects a store instruction for data in a processor where the store instruction is a reliable indicator of a future load for the data; in response to detecting the store instruction, sends a prefetch request to memory for an entire cache line containing the data referenced in the store instruction, and preferably only the single cache line containing the data; and receives, in response to the prefetch request, the entire cache line containing the data referenced in the store instruction.

Store prefetches for dependent loads in a processor

An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; a Page Walk Cache (PWC) for storing page directory entries; and a memory controller configured to control accesses to the memory devices. The processor in an embodiment is configured to send to the memory controller a page directory base and a plurality of memory offsets; and receive from the memory controller and store in the PWC at least one of the page directory entries. The memory controller is configured to: combine a first level page directory entry with a second level memory offset; read from memory a second page directory entry using the first level page directory entry and the second level memory offset; and send to the processor at least one of the page directory entries and a page table entry (PTE).

Growing community of inventors

Austin, TX, United States of America

Mohit Karve