International Business Machines Corporation

Mohit Kapur

Sameh W Asaad

Dimitrios Pendarakis

Richard Harold Boivie

Kenneth Alan Goldman

Enriquillo Valdez

Peter Grimm Sutton

Donna N Dillenberger

John C Dayka

James Alan Ruddy

Alyson Comer

Seongwon Kim

Jose A Tierno

William Eric Hall

Kattamuri Ekanadham

David R Safford

Peter Anthony Sandon

Bharat Sukhwani

Bhushan Pradip Jain

Bernard V Brezzo

Benjamin D Parker

Muir Kumph

Charles Louis Haymes

Guerney Douglass Holloway Hunt

Jiri Stehlik

Ralph E Bellofatto

Enriquilo Valdez

Sameth W Asaad

Thomas Roewer

Guerney D Hunt

A computer-implemented method, system and computer program product for minimizing hash collisions of composite keys. Each component ('key component') of the composite key is converted into a linear index that uniquely represents that key component. Such a one-to-one mapping reduces the length (i.e., range of values the key component represents) of each component without introducing any collisions thereby effectively resulting in the lossless compression of the individual key components. Such a linear index for each converted key component is stored in a separate lookup memory. A reduced composite key is then created by joining together the linear indices that represent the components of the composite key thereby reducing the total length or domain (i.e., range of values the composite key represents) of the original composite key in a lossless manner. In this manner, by reducing the total length of the composite key, hash collisions of composite keys are minimized.

Minimizing hash collisions of composite keys

Managing hardware function requests incurring variable response latencies is provided. A request for a hardware function is received from a requesting program. The requested hardware function is expected to incur a variable response latency and is implemented as a main hardware function and a retry hardware function. The main hardware function is executed. It is determined whether a fixed response latency of the main hardware function has been exceeded. A response is returned with a retry flag to the requesting program. The retry flag directs the requesting program to issue a request for the retry hardware function after an interval of time. A unique identifier corresponding to the main hardware function is provided to the requesting program.

Non-blocking hardware function request retries to address response latency variabilities

An apparatus, system and method for protecting the confidentiality and integrity of a secure object running on a computer system by protecting the memory pages owned by the secure object, including assigning a secure object an ID, labeling the memory pages owned by a secure object with the ID of the secure object, maintaining an Access Control Monitor (ACM) table for the memory pages on the system, controlling access to memory pages by monitoring load and store instructions and comparing information in the ACM table with the ID of the software that is executing these instructions; and limiting access to a memory page to the owner of the memory page.

System and method for supporting secure objects using a memory access control monitor

A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Embodiments include techniques for transmitting and receiving radio frequency (RF) signals, where the techniques for generating, via a digital analog converter (DAC), a frequency signal, and filtering the frequency signal to produce a first filtered signal and a second filtered signal. The techniques also include transmitting the second filtered signal to a device under test, and filtering the second filtered signal into a sub-signal having one or more components. The techniques include mixing the first filtered signal with the sub-signal to produce a first mixed signal, subsequently mixing the first mixed signal with an output signal received from the device under test to produce a second mixed signal, and converting the second mixed signal for analysis.

Transmit and receive radio frequency (RF) signals without the use of baseband generators and local oscillators for up conversion and down conversion

A processor-implemented method for a secure processing environment for protecting sensitive information is provided. The processor-implemented method may include receiving encrypted data and routing the encrypted data to the secure processing environment. Then the encrypted data may be decrypted and fields containing sensitive information may be found. The method may also include obfuscating the sensitive information and returning, by the secure processing environment, the decrypted data and obfuscated data.

Secure processing environment for protecting sensitive information

An aspect includes a direct digital synthesis system including a waveform generator with a waveform memory operable to store a plurality of waveform vectors and output a selected waveform vector. The direct digital synthesis system also includes a digital-to-analog converter operable to convert the selected waveform vector from a digital value to an analog signal responsive to a reference clock. The direct digital synthesis system further includes a controller operable to maintain phase continuity of the analog signal when an output of the analog signal is interrupted and restored.

Phase continuous signal generation using direct digital synthesis

A processor in a computer system, the processor including a mechanism supporting a Secure Object that comprises information that is protected so that other software on said computer system cannot access or undetectably tamper with said information, thereby protecting both a confidentiality and an integrity of the Secure Object information while making the Secure Object information available to the Secure Object itself during execution of the Secure Object. The mechanism includes a crypto mechanism that decrypts and integrity-checks Secure Object information as said Secure Object information moves into the computer system from an external storage system, and encrypts and updates an integrity value for Secure Object information as said Secure Object information moves out of the computer system to the external storage system, and a memory protection mechanism that protects the confidentiality and integrity of Secure Object information when that information is in the memory of the computer system.

Growing community of inventors

Sleepy Hollow, NY, United States of America

Mohit Kapur