Netapp, Inc.

Sifive, Inc.

Pure Storage, Inc.

Alphawave Semi, Inc.

Mohit Gupta

Ravikanth Dronamraju

Sriram Venketaraman

Santosh Mahadeo Narawade

Jithin K

Ananthan Subramanian

Subramaniam Periyagaram

Ram Kesavan

Joshua Freilich

Mrinal K Bhattacharjee

Kyle Diggs Sterling

Manpreet Singh

Riley Thomasson

Robert M English

Andrew G Tucker

Eric P Forgette

Jose Mathew

Varun Jobanputra

Sisir Shekhar

Vishwajith Shivappa

Vania N Fang

Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.

Composite aggregate architecture

Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold.

Low-swing Schmitt triggers

Systems and methods are disclosed for wide frequency range voltage controlled oscillators. For example, an apparatus includes a Voltage Controlled Oscillator (VCO) including a delay cell which includes first and second current sources provided in parallel with one another. The first current source is controlled by a voltage control input connected to a voltage control terminal and the second current source is controlled by a bias voltage input connected to a bias voltage terminal. The first current source provides an alternate current path in the delay cell when the second current source is off. The delay cell is operable to receive an input and produce an output using the alternate current path.

Wide frequency range voltage controlled oscillator

A first read request for data stored at a non-volatile memory is received by a primary storage controller. The data is programmed from the non-volatile memory to a first cache of the primary storage controller, the first cache to store the data over a first time range. A second read request is received for the data. In response to receiving the second read request for the data, the data is programmed to a second cache to store the data over a second time range that is greater than the first time range. A notification is transmitted to a secondary storage controller, the notification including information associated with the programming of the data to the second cache.

Tiered caching of data in a storage system

Techniques are provided for selectively storing data into allocation areas using streams. A set of allocation areas (e.g., ranges of block numbers such as virtual block numbers) are defined for a storage device. Data having particular characteristics (e.g., user data, metadata, hot data, cold data, randomly accessed data, sequentially accessed data, etc.) will be sent to the storage device for selective storage in corresponding allocation areas. For example, when a file system receives a write stream of hot data, the hot data may be assigned to a stream. The stream will be tagged using a stream identifier that is used as an indicator to the storage device to process data of the stream using an allocation area defined for hot data. In this way, data having different characteristics will be stored/confined within particular allocation areas of the storage device to reduce fragmentation and write amplification.

Selectively storing data into allocation areas using streams

Described is a delay-locked loop which includes a frontend circuit configured to output a control voltage based on an input clock and a feedback clock and a delay line circuit connected to the frontend circuit. The delay line circuit configured to generate a bias voltage based on the control voltage and a step size, where the bias voltage is variable based on the step size, and apply at least one level of delay on the input clock based on the bias voltage to generate an output clock, where the feedback clock being based on the output clock and where the input clock is aligned with the feedback clock by delaying the phase of the output clock until phase lock.

Wide frequency range step size programmability for delay-locked loops using variable bias voltage generation

Described is a high speed, low power level shifter circuit which includes a level shifter coupled to a sensing circuit. The level shifter includes a pair of source transistors, a pair of input transistors, and a pair of switching circuits connected between the source transistors and the input transistors. The sensing circuit turns off a switching circuit on an active side of the level shifter based on detecting that an output voltage of the level shifter has completed a voltage level transition from a first logic level voltage to a second logic level voltage. An open circuit is established on the active side and turns off the pair of source transistors. The other switching circuit is turned on. Static current flow on the active side of the level shifter is stopped and the output voltage is latched to a voltage representative of the second logic level voltage.

Zero static high-speed, low power level shifter

Described is a high speed, low power level shifter circuit which includes a cross-coupled level shifter coupled to a sensing circuit. The sensing circuit turns off a cross-coupled node of a pair of cross-coupled nodes based on detecting that an input voltage has crossed a threshold voltage for a cross-coupled input transistor of a pair of cross-coupled input transistors, i.e. due to switching from a current logic level to an incoming logic level. Once the sensing circuit detects a threshold voltage crossing, a pull-up circuit pulls high a cross-coupled node and cross-coupled source transistor tied to the cross-coupled node. This turns off the cross-coupled source transistor and turns on another cross-coupled source transistor. Two parallel paths are now established to pull the cross-coupled node high, enabling a high-speed transition. The turning off of the cross-coupled source transistor also pulls the output to the incoming logic level.

Cross-coupled high-speed, low power level shifter

Systems, methods, and computer program products implementing hybrid file structures for data storage are provided. One embodiment of a method performed in a computer-based storage system includes writing a file as data blocks in an array of storage devices. The method includes associating the data blocks with metadata related to at least one location in the array of storage devices for later access to the data blocks. The file is represented as a hierarchical data structure having a plurality of nodes. A first portion of nodes has a first span type, and a second portion of nodes has a second span type. The data structure includes a buftree. The first span type includes a fixed-span type. The second span type includes a variable-span type.

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San Jose, CA, United States of America

Mohit Gupta