International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Mohit Bajaj

Rajan K Pandey

Kota V R M Murali

Edward J Nowak

Aniruddha Konar

Terence B Hook

Rajesh Sathiyanarayanan

Takashi Ando

Suresh Gundapaneni

Narasimha R Mavilla

Kumar R Virwani

Arpan K Deb

Rahul Nayak

Peter Javorka

Geoffrey W Burr

Samarth Agarwal

Ali Icel

Ram Asra

Avinash Lahgere

Prashanth Paramahans Manik

A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (I) without affecting the on-state current (I), and thus an improved I/Iratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.

Transistor with phase transition material region between channel region and each source/drain region

A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.

Logic layout with reduced area and method of making the same

A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer

A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Stable work function for narrow-pitch devices

The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VOregion.

Symmetric tunnel field effect transistor

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

Tunable voltage margin access diodes

Growing community of inventors

Bengaluru, India

Mohit Bajaj