Oracle International Corporation

Mohd Jamil Mohd

Ali Vahidsafa

Krishnan Sundaresan

Alan Smith

Aravind Oommen

Senthilkumar Diraviam

Yibin Xia

Pranjal Srivastava

Hemanga Lal Das

Dinesh Rajasavari Amirtharaj

A method for simulating a power consumption associated with a circuit. Once a netlist describing the circuit and an input stimulus for the netlist are obtained, the netlist is partitioned into multiple circuit blocks. Circuit logic models (CLMs) implemented in a hardware description language (HDL) are then obtained for the multiple circuit blocks and a logic netlist is generated from the multiple CLMs. A power vector for a CLM corresponding to a circuit block is calculated using a logic simulator inputting the logic netlist and the input stimulus. Further, a power consumption value is calculated for the circuit block using a circuit simulator and the power vector. The power consumption associated with the circuit is calculated based on the power consumption values for various circuit blocks.

Custom circuit power analysis

Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Unified tool for automatic design constraints generation and verification

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Santa Clara, CA, United States of America

Mohd Jamil Mohd