Marvell Asia Pte., Ltd.

Lattice Semiconductor Corporation

Mohana Tandyala

Ulf Hanebutte

Senad Durakovic

Fu-Hwa Wang

Chien-Chun Chou

Hua Xue

Venkatesan Rajappan

Sunil Sharma

A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.

Multistage compiler architecture

A method includes determining that an amount of data external to an inference engine to be transmitted for local storage/processing by a first processing tile exceeds an available space at a first OCM of the first processing tile; receiving a first portion of the data at the first processing tile; transmitting the first portion of the data to a second OCM of a second processing tile for temporary local storage (the second processing tile is within the inference engine); receiving and storing a second portion of the data at the first OCM; processing the second portion of the data at the first processing tile by at least a first processing element; receiving and storing the first portion of the data at the first OCM of the first processing tile from the second processing tile prior to the first portion of data is needed by the first processing tile.

Method and system to expand accessible on-chip memory (OCM) of an inference engine

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation.

Efficient constant multiplier implementation for programmable logic devices

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.

Growing community of inventors

Fremont, CA, United States of America

Mohana Tandyala