Intel Corporation

Mohan Nair

Michael T Klinglesmith

Joseph Murray

Utkarsh Y Kakaiya

Pratik M Marolia

Blaise B Fanning

Mikal Hunsaker

Sridhar Lakshmanamurthy

Robert P Adler

David M Lee

Rohit R Verma

Gary J Lavelle

Rajesh M Sankaran

James W Alexander

Brian S Morris

Joshua David Fender

Malay Trivedi

Chih-Cheh Chen

Itay Franko

Peter J Elardo

John Zulauf

Mahesh S Natu

Devadatta V Bodas

Ishwar Agarwal

Ramamurthy Krithivas

Brent D Thomas

Nagabhushan Chitlur

Buck Gremel

Pinkesh J Shah

Nitish Paliwal

Peeyush Purohit

Christopher Van Beek

Minjer Juan

Rahul Boyapati

Vijay Pothi Raj Govindaraj

Chris Van Beek

Vijayendra K Hoskoti

Zhenfu Chai

A circuit system includes slow running logic circuitry that generates write data and a write command for a write request. The circuit system also includes fast running logic circuitry that receives the write data and the write command from the slow running logic circuitry. The fast running logic circuitry stores the write data and the write command. A host system generates a write response in response to receiving the write command from the fast running logic circuitry. The host system sends the write response to the fast running logic circuitry. The fast running logic circuitry sends the write data to the host system in response to receiving the write response from the host system before providing the write response to the slow running logic circuitry.

Circuits and methods for coherent writing to host systems

Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

Securely exposing an accelerator to privileged system components

There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.

Unified address space for multiple links

In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.

Extending a root complex to encompass an external component

This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric includes a management device and a network fabric coupled thereto. A plurality of virtual endpoint devices are coupled to the network fabric and are configured to connect with a plurality of compute nodes. In addition, the intelligent network fabric includes a root port device coupled to the network fabric which the root port is configured to connect with virtual functions within a SR-IOV device.

Intelligent network fabric to connect multiple computer nodes with one or more SR-IOV devices

In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.

Method, apparatus and system for encapsulating information in a communication

In one embodiment, a system comprises: a plurality of compute nodes having a first core, a first memory, and a first fabric; a plurality of input/output (I/O) nodes having a second core, a second memory, and a second fabric and to couple to one or more I/O devices; at least one management node to receive discovery information responsive to execution of a discovery process by the plurality of compute nodes and the plurality of I/O nodes. The discovery information may include resource request information from the plurality of compute nodes and resource availability information from the plurality of I/O nodes. The at least one management node may configure the plurality of compute nodes and the plurality of I/O nodes based thereon. The system may further include an interconnection fabric to couple the plurality of compute nodes, the plurality of I/O nodes, and the at least one management node, where the at least one management node is to enable the one or more I/O devices to be shared between at least some of the plurality of compute nodes based on the discovery information. Other embodiments are described and claimed.

Method, apparatus and system for automatically discovering nodes and resources in a multi-node system

In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

Systems and an apparatus with a sideband interface interconnecting agents with at least one router

A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system.

Method and system for platform management messages across peripheral component interconnect express (PCIe) segments

Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein.

Dynamic link width adjustment

Aggregating completion messages in a sideband interface

In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed.

Flexibly integrating endpoint logic into varied platforms

An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.

Method and apparatus for optimizing power and latency on a link

Devices and method with hardware configured to support phantom register programming. Where phantom register programming allows a device driver for an endpoint device to program multicast registers in the device without support of the operating system.

Multicast support on a switch for PCIe endpoint devices

Growing community of inventors

Portland, OR, United States of America

Mohan Nair