Texas Instruments Corporation

Mohan Mishra

Stephen Wayne Spriggs

Bryan David Sheffield

Suresh Balasubramanian

George B Jamison

Suresh Balasuramanian

The memory array contains two layers representing word lines of different rows. Each row contains multiple bit cells sharing the same word line. The two layers are stacked one on top of another to form a high density memory array.

High density memory array

An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable signal. A tracking circuit generates the latch enable signal in an appropriate time window. The tracking circuit may contain a dummy sense amplifier implemented similar to the actual sense amplifier and a dummy column from which the actual sense amplifier senses a signal received upon accessing the dummy memory array. The latch enable signal may be generated after the dummy sense amplifier generates a bit representing the sensed signal. The time taken by the dummy sense amplifier to generate the bit depends on the load offered by the dummy memory array. Accordingly, the dummy memory array is designed to offer sufficient load to ensure that the latch enable signal is generated in an appropriate time window.

Tracking circuit enabling quick/accurate retrieval of data stored in a memory array

A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if current is not present. As the sense amplifier can be implemented to generate such logical values with a current signal of low strength, memory arrays with correspondingly low drive strength can be implemented. As a result, memory systems which consume minimal power and having high density can be provided. In addition, as the sense amplifiers can operate without any reference signals, the implementation of sense amplifiers may be simplified.

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Madhubani, India

Mohan Mishra