Achronix Semiconductor Corporation

Mohan Krishna Vedam

Virantha N Ekanayake

Christopher C LaFrieda

Sarma Jonnavithula

Namit Varma

Naresh Sharma

Kent Orthner

Pavan Kumar Kasibhatla

A sliced router decomposes a router into a plurality of slices. Each slice has a subset of the input and output ports of the router. One or more of the slices may communicate with a network access point. Adjacent slices communicate with each other. In some example embodiments, there are dedicated physical channels between each slice and each adjacent slice for traffic coming in on or going out on ports of other slices. Within a slice, traffic may be arbitrated onto upstream or downstream channels going to the same output port. Each slice contains one or more crossbars, allowing data received on any input port to be routed to any output port of the slice. The crossbar of each slice is substantially smaller than the crossbar that would be used by a unified router.

Sliced router for network on a chip

Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Synchronous reset deassertion circuit

A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.

Wide elastic buffer

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Karantaka, India

Mohan Krishna Vedam