Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sandisk Corporation

Mohan Dunga

Masaaki Higashitani

Changyuan Chen

Biswajit Ray

Pitamber Shukla

Peter Rabkin

Venkatesh Ramachandra

Piyush Dak

Luisa Lin

Deepanshu Dutta

Man Lung Mui

Fumiaki Toyama

Gerrit Jan Hemink

Anubhav Khandelwal

Yan Li

Nima Mokhlesi

Xiang Yang

Niles Yang

Yingda Dong

James K Kai

Tuan Duc Pham

Yuki Mizutani

Chia-Lin Hsiung

Chris Yip

Wendy Ou

Sanghyun Lee

Himanshu Hemant Naik

Nian Niles Yang

Zhenming Zhou

Jiahui Yuan

Jayavel Pachamuthu

Huai-Yuan Tseng

Franz Kreupl

Wei Zhao

Grishma Shah

Hao Nguyen

Sahil Sharma

Rohit Sehgal

Sarath Chandran Puthenthermadam

Kwang-Ho Kim

Muhammad Masuduzzaman

Philip David Reusswig

Phil Reusswig

Zhenyu Lu

Jongsun Sel

Sourabh Sankule

Joanna Lai

Piyush Girish Sagdeo

Shiqian Shao

Katsuo Yamada

Tomoyasu Kakegawa

Keyur Payak

Chia-Kai Chou

Satoru Mayuzumi

Bijesh Rajamohanan

Sudarshan Narayanan

Abuzer Azo Dogan

Chao Qin

Lishan Weng

A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines. Some of the word line switch transistors have a first width and some of the word line switch transistors have a second width that is different than the first width. By providing the word line switch transistors with different widths, the size of a word line switch area in the memory device can be optimized.

Word line dependent word line switch design and programming techniques

A memory apparatus and method of operation are provided. The apparatus includes word line switches coupled to word lines connected to memory cells. The word line switches are each configured to retain a switch threshold voltage and selectively connect the word lines to a common driver for supplying voltages thereto during a memory operation. A control means is configured to apply predetermined select block switch voltages to a first set of the word line switches connected to the word lines of a selected block. The predetermined select block switch voltages are based on the memory operation performed. The control means apply a predetermined unselect block switch voltage to a second set of the word line switches connected to the word lines of an unselected block. The predetermined unselect block switch voltage is selected to lower the switch threshold voltage of the word line switches of the second set.

Unselect word line switch bias scheme for non-volatile memory apparatus

A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

Non-volatile memory with capacitors using metal under signal line or above a device capacitor

A non-volatile memory includes a non-volatile memory array comprising blocks of non-volatile memory cells, bit lines connected to the memory cells and word lines connected to the memory cells. Word line switch transistors connect the word lines to voltage sources. The word line switch transistors are positioned in triple wells. Multiple triple wells are utilized and the word line switch transistors are grouped into triple wells based on word line voltage ranges used during the programming process. In one embodiment, for a given block, the word line switch transistors connected to data word lines are positioned in a first triple well and the word line switch transistors connected to selection and dummy word lines are positioned in a second triple well. This structure allows the triple wells to be biased differently.

Non-volatile memory with multiple wells for word line switch transistors

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, where each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, drain regions contacting an upper end of a respective one of the vertical semiconductor channels, first contact via structures directly contacting a first subset of the drain regions and each having a first horizontal cross-sectional area, and second contact via structures directly contacting a second subset of the drain regions and each having a second horizontal cross-sectional area that is greater than the first horizontal cross-sectional area.

Three-dimensional memory device containing multiple size drain contact via structures and method of making same

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

Non-volatile memory with fast partial page operation

Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.

Temperature based programming in memory

Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

Programming to minimize cross-temperature threshold voltage widening

The storage device comprises a non-volatile memory coupled to a controller. The controller is configured to determine a first programming voltage by performing at least one program-verify iteration on a first word line using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed. The controller is also configured to determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount. The controller is further configured to perform at least one program-verify iteration on a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.

Wordline smart tracking verify

A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

Systems and methods for high-performance write operations

A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

Non-volatile memory with pool capacitor

A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Post write erase conditioning

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Santa Clara, CA, United States of America

Mohan Dunga