Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Mohammed Rahim Chand Seikh

Dharmendra Kumar Rai

Manish Umedlal Patel

Mohit Gupta

Bijan Kumar Ghosh

An accelerator circuit is provided that includes an inverter chain having an input coupled to a data line and a sense circuit having inputs coupled to an output of the inverter chain and the data line. The sense circuit is configured to sense a rise toward a supply voltage on the data line or a fall toward a ground voltage on the data line. The accelerator circuit further includes an amplify circuit having inputs coupled to outputs of the sense circuit and an output coupled to the data line, where the amplify circuit is configured to amplify the data line toward the supply voltage or toward the ground voltage based on amplify enable signals output by the sense circuit.

Read accelerator circuit

A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.

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Bengaluru, India

Mohammed Rahim Chand Seikh