Texas Instruments Corporation

Mohammed Nabeel

Saket Jalan

Sudesh Chandra Srivastava

In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

Methods and apparatus for reduced area control register circuit

A device includes a plurality of functional logic blocks, a cascaded arrangement of multiplexers and a digital counter. Each of the plurality of functional logic blocks outputs a signals corresponding to nodes to be tested therein. The cascaded arrangement of multiplexers are arranged such that any of the outputs from any of the plurality of functional logic blocks may be selected for output. The digital counter is operable to control the cascaded arrangement of multiplexers so as to output signals from the functional logic blocks based on a counted signal.

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Bengaluru, India

Mohammed Nabeel