International Business Machines Corporation

Infineon Technologies Ag

Other

Mohammed Fazil Fayaz

Anthony K Stamper

Daniel Scott Vanslette

Andy Cowley

Jeffery Burton Maxson

Haining S Yang

Laertis Economikos

Conal Eugene Murray

Ruchir Puri

William Thomas Motsiff

Stephen Edward Greco

Mark Hoinkis

Ismail C Noyan

Hua Xiang

Leah M Pastel

Maroun Kassab

Gerald R Friese

Steffen K Kaldor

Patricia A O'Neil

Paul Wensley

Joseph J Mezzapelle

Uwe Kerst

Martin Commons

Matthias P Hierlemann

Julie L Lee

Erdum Kaltalioglu

Anne L Petrosky

Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.

Methods for controlling wafer curvature

Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

Identifying defects

Methods and structures for controlling wafer curvature

Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design

A method, apparatus, and computer program product for flattening a warped substrate. The substrate is placed on a planar surface of a clamping apparatus in direct mechanical contact with the planar surface. The substrate comprises surface regions S, S, . . . , Shaving an average warpage of W, W, . . . , W, respectively, wherein W&#x2266;W&#x2266; . . . &#x2266;Wand W&#x2266;W. Zones Z, Z, . . . , Zof the planar surface respectively comprise vacuum port groups G, G, . . . , G. Each group comprises at least one vacuum port. N is at least 2. A vacuum pressure P, P, . . . , Pis generated at each vacuum port within group G, G, . . . , G, at a time of T, T, . . . , Tto clamp surface region S, S, . . . , Sto zone Z, Z, . . . , Z, respectively. The vacuum pressure P, P, . . . , Pis maintained at the vacuum ports of group G, G, . . . , G, respectively, until time T. T&#x3c;T&#x3c; . . . &#x3c;T&#x3c;T.

Apparatus and method for flattening a warped substrate

The act of blowing an unpassivated electrical fuse (for example, fuse) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.

Reduced splattering of unpassivated laser fuses

Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a predetermined value below which the additional stress on the vias does not significantly increase.

Via density rules

A memory device and method of manufacturing thereof, wherein a silicide material is selectively formed over active regions of a memory device. A silicide material may also be formed on the top surface of wordlines adjacent the active regions during the selective silicidation process. A single nitride insulating layer is used, and portions of the workpiece are covered with photoresist during the formation of the silicide material.

Selective silicidation scheme for memory devices

A MIM capacitor includes a bottom plate, a capacitor dielectric disposed over the bottom plate, and a top plate disposed over the capacitor dielectric. An etch stop material is disposed over the top plate, and the top plate has a width that is less than the width of the etch stop material width. The top plate edges may be pulled back during the removal of the resist used to pattern the top plate, by the addition of chemistries in the resist etch that are adapted to pull-back or undercut the top plate edges beneath the etch stop material.

MIMcap top plate pull-back

Growing community of inventors

Pleasantville, NY, United States of America

Mohammed Fazil Fayaz