Advanced Micro Devices Corporation

Mohammed Anjum

Ibrahim K Burki

Craig William Christian

Maung H Kyaw

Klaus H Koop

Alan L Stuber

John K Lowell

Norman L Armour

Valerie A Wenner

An MOS device is provided having a channel-stop implant placed between active regions and beneath field oxides. The channel-stop dopant material is a p-type material of atomic weight greater than boron, and preferably utilizes solely indium ions. The indium ions, once implanted, have a greater tendency to remain in their position than boron ions. Subsequent temperature cycles caused by, for example, field oxide growth do not significantly change the initial implant position. Thus, NMOS devices utilizing indium channel-stop dopant can achieve higher pn junction breakdown voltages and lower parasitic source/drain-to-substrate capacitances. Furthermore, the heavier indium ions can be more accurately placed than lighter boron ions to a region just below the silicon layer which is to be consumed by subsequent field oxide growth. By fixing the peak concentration density of indium at a depth just below the field oxide lower surface, channel-stop implant region is very shallow. Small dispersions in range allow for more precise control of the indium atoms just below the field oxide, further from the inner bulk material of the underlying substrate.

Semiconductor field region implant methodology

An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

Active region implant methodology using indium to enhance short channel performance of a surface channel PMOS device

A field oxide is provided which purposefully takes advantage of fluorine mobility from an implanted impurity species. The field oxide can be enhanced or thickened according to the size (area and thickness) of the oxide. Fluorine from the impurity species provides for dislodgement of oxygen at silicon-oxygen bond sites, leading to oxygen recombination at the field oxide/substrate interface. Thickening of the oxide through recombination occurs after it is initially grown and implanted. Accordingly, initial thermal oxidation can be shortened to enhance throughput. The fluorine-enhanced thickening effect can therefore compensate for the shorter thermal oxidation time. Moreover, the thickened oxide regions are anistropically oxidized underneath existing thermally grown oxides and directly underneath openings between nitrides. The thickened oxides therefore do not cause additional shrinkage of the active areas which reside between field oxides.

Semicondutor having selectively enhanced field oxide areas and method

A PMOS device is provided having a diffusion barrier placed within the polysilicon gate. The diffusion barrier is purposefully deposited to a concentration peak density within the gate which is deeper than subsequently placed impurity dopant. The barrier comprises germanium atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises an ionized compound of BF.sub.2 subsequently placed as boron within the gate and source/drain region, at least a majority and preferably greater than eighty percent of which are placed shallower within the gate than the germanium atoms. The barrier region substantially prevents or retards penetration of boron atoms through the gate oxide and into the channel region. Thus, the barrier helps prevent change in channel concentration and problems associated with boron penetration such as flatband voltage (Vfb) and threshold voltage (Vth) shift.

Method for producing a semiconductor gate conductor having an impurity

A semiconductor structure with large tile angle boron implant is provided for reducing threshold shifts or rolloff at the channel edges. By minimizing threshold shifts, short channel effects and subthreshold currents at or near the substrate surface are lessened. The semiconductor structure is prepared by implanting boron at a non-perpendicular into the juncture between the channel and the source/drain as well as the juncture between the field areas and the source/drain. Placement of boron into these critical regions replenishes segregating and redistributing threshold adjust implant species and channel stop implant species resulting from process temperature cycles. Using lighter boron ions allow for a lesser annealing temperature and thereby avoids the disadvantages of enhanced redistribution and diffusion caused by high temperature anneal.

Large tilt angle boron implant methodology for reducing subthreshold

An improved method is provided for fabricating a metal silicide upon a semiconductor substrate. The method advantageously places a film of metal nitride upon the metal layer. The metal nitride layer and metal layer are sputter deposited within the same chamber without removing the substrate from the vacuum so as to prevent oxygen or moisture from contaminating the metal layer and causing oxides to form thereon. Furthermore, the metal nitride layer is reactively sputter deposited in a nitrogen/argon ambient to allow precise amounts of nitrogen to be deposited across uneven surface topography directly adjacent to the underlying metal layer. Excess nitrogen purposefully deposited within the metal nitride layer consumes a controlled depth of metal bond sites within the underlying metal layer so as to limit the amount of silicidation from underlying silicon or polysilicon into the metal thereby substantially eliminating or minimizing silicide shorting problems.

Integrated circuit fabrication using a metal silicide having a

A method and device is provided for determining defects within a single crystal substrate. The methodology includes a surface photovoltage (SPV) technique in which the magnitude of non-linearity is quantified and correlated to defects within the crystal lattice. The correlation factor is determined in a rapid and efficient manner using least square correlation methodology without having to determine diffusion length and incur difficulties associated therewith. Obtaining a quantifiable least square correlation factor allows the operator to quickly determine the amount of crystalline damage often encountered by, for example, ion implantation. In addition, the operator can determine the relative depth and position of defective crystalline layers within the substrate based upon demarcations between monotonically and non-monotonically aligned points plotted in a graph of reciprocal photovoltage versus reciprocal absorption coefficient.

Method and device for determining defects within a crystallographic

An improved method is provided for fabricating a metal silicide upon a semiconductor substrate. The method utilizes ion beam mixing by implanting germanium to a specific elevation level within a metal layer overlying a silicon contact region. The implanted germanium atoms impact upon and move a plurality of metal atoms through the metal-silicon interface and into a region residing immediately below the silicon (or polysilicon) surface. The metal atoms can therefore bond with silicon atoms to cause a pre-mixing of metal with silicon near the interface in order to enhance silicidation. Germanium is advantageously chosen as the irradiating species to ensure proper placement of the germanium and ensuing movement of dislodged metal atoms necessary for minimizing oxides left in the contact windows and lattice damage within the underlying silicon (or polysilicon).

Method for forming a silicide using ion beam mixing

A method is provided for controlling growth of silicide to a defined thickness based upon the relative position of peak concentration density depth within a layer of titanium. The titanium layer is deposited over silicon and namely over the silicon junction regions. Thereafter the titanium is implanted with argon ions. The argon ions are implanted at a peak concentration density level corresponding to a depth relative to the upper surface of the titanium. The peak concentration density depth can vary depending upon the dosage and implant energies of the ion implanter. Preferably, the peak concentration density depth is at a midpoint between the upper and lower surfaces of the titanium or at an elevational level beneath the midpoint and above the lower surface of the titanium. Subsequent anneal of the argon-implanted titanium causes the argon atoms to occupy a diffusion area normally taken by silicon consumed and growing within overlying titanium. However, based upon the presence of argon, the diffusion length and therefore the silicide thickness is reduced to a controllable amount necessary for applications with ultra-shallow junction depths.

Method for low energy implantation of argon to control titanium silicide

An enhanced capacitor configuration is provided in which the conductive and insulative layers are formed by implantation rather than deposition. The conductive regions are implanted at dissimilar depths and the insulative region is implanted between the conductive regions to form the conductive plates and intermediate dielectric material. By implanting rather than depositing, the dielectric material remains free of pinholes and can be configured thinner than conventional dielectrics, with a higher dielectric constant (k) due to the absence of an oxide. Moreover, cross-diffusions which occur during the anneal step allow texturization of the dielectric/conductive juncture. Texturization corresponds to an increase in surface area of the capacitor and, similar to increase in dielectric constant and decrease in dielectric thickness, increases the capacitive value of the ensuing capacitor.

Method of fabricating a capacitor with a textured polysilicon interface

A method is provided for reducing growth of silicide and the temperatures necessary to produce silicide. Germanium is implanted at a concentration peak density depth below the midline and above the lower surface of a metal layer receiving the implant. Subsequent anneal causes germanide to occupy an area above growing silicide such that consumption of silicon atoms is reduced, and that silicide is formed to a controlled thickness.

Germanium implant for use with ultra-shallow junctions

A PMOS device is provided having a diffusion barrier placed within a polysilicon gate material. The diffusion barrier is purposefully implanted to a deeper depth within the gate material than subsequently placed impurity dopants. The barrier comprises Ar atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises ions of BF.sub.2. F from the impurity dopant of BF.sub.2 is prevented from diffusing to underlying silicon-oxide bonds residing within the oxide bulk. By minimizing F migration to the bond sites, the present polysilicon barrier and method of manufacture can minimize oxygen dislodgment and recombination at the interface regions between the polysilicon and the gate oxide as well as between the gate oxide and silicon substrate.

Method of fabricating semiconductor gate electrode with fluorine

Method of making a semiconductor having selectively enhanced field oxide

A semiconductor structure with germanium implant is provided for reducing V.sub.T shifts at the channel edges thereby minimizing short channel effects and subthreshold currents at or near the substrate surface. The semiconductor structure is adapted to receive non-perpendicular implant of germanium in the juncture between the channel and the source/drain regions as well as in the juncture between field oxide channel stop implant and source/drain regions. By carefully and controllably placing the germanium at select channel and field regions, segregation and redistribution of threshold adjust implant and channel stop implant dopant materials is substantially minimized. Reducing the redistribution of such materials provides a reduction in the short channel effects and, particularly, a reduction in substrate surface current or DIBL-induced current.

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Austin, TX, United States of America

Mohammed Anjum