Telefonaktiebolaget Lm Ericsson (publ)

Mohammed Abdulaziz

Henrik Sjöland

Tony Påhlsson

Alexander Hunt

Andreas Kristensson

Mohammed Zourob

Bryan Smith

Waqas Ahmad

Henrik Pia Sjöland

A technique for performing partial reads of a touch sensor () provides several advantages, including scalability to touch sensors with high sensing-line counts, and reductions in operating power. The technique involves identifying a region () of the touch surface () of the touch sensor () to be read and performing a partial read directed to the identified region. Rather than exciting all sensing lines of the touch surface (), the partial read excites one or more of the sensing lines () that are involved with the identified region (), without exciting one or more of the uninvolved sensing lines (). Identifying the region or regions () to be read involves, for example, obtaining touch-control information from a software application () running on a host device () that includes the touch sensor ().

Method and apparatus for performing partial reads of a touch sensor

An apparatus () and method () provide power-efficient reading of a touch sensor () by performing transform-based reading of the touch sensor () according to a read configuration () that accounts for touch-surface areas that are indicated as touch targets () for receiving touch input. Advantages such as power savings and more robust touch detection flow from the intelligent selection of which sensing lines () of the touch sensor () to excite and which excitation frequencies () to use for exciting them.

Method and apparatus for interfacing with a touch sensor

Methods () and apparatuses () disclosed herein embody a technique for reading a touch sensor () that provides several advantages, including scalability to touch sensors with high column/row counts and reductions in operating power. 'Reading' in this context refers to the application of one or more excitation frequencies to one or more column lines () and row lines () used for detecting touch inputs to a touch surface () of the touch sensor (), along with the corresponding transformation of the resulting sensing signals into frequency domain values and evaluation of the values () corresponding to the excitation frequencies. The technique in an example implementation involves a hierarchical reading scheme that divides the touch surface (), or any portion thereof, into regions, and performs initial touch detection at the per-region resolution, with subsequent higher-resolution reading of at least the region(s) where touch inputs have been detected.

A technique for reading the columns and rows of a touch sensor provides several advantages, including scalability to touch sensors with high column/row counts. Reading the touch sensor relies on combining the row or column outputs of the touch sensor, during column and/or row excitation of the touch sensor, with the resulting combined signal or signals transformed into the frequency domain and touch detection based on evaluation of the frequency-domain values corresponding to the excitation frequencies.

An apparatus is disclosed for provision of an indication of an angular difference between first and second input signals. The apparatus comprises a phase frequency detector (PFD) configured to receive the first and second input signals and to provide first and second outputs based on the first and second input signals. A difference in pulse length between signals provided at the first and second outputs is indicative of the phase difference between the first and second input signals. The apparatus also comprises first and second time-to-digital converters (TDCs) each configured to receive one of the signals provided by the PFD and to provide a corresponding digital pulse length representation. Each of the TDCs is a pulse length modifying TDC, wherein pulse length modification may comprise pulse length shrinking or pulse length extension. The apparatus also comprises a comparator configured to provide the indication of the phase difference based on the digital pulse length representations provided by the first and second TDCs. Corresponding digital phase-locked loop (DPLL) and communication device are also disclosed.

Apparatus for digital representation of angular difference

The present application concerns a tunable differential transmission line segment, comprising a differential pair of signal line segments () arranged in a first plane. A pair of tuning line segments () is arranged in a second plane substantially parallel to the first plane, wherein the pair of tuning line segments () is at least capacitively coupled to the differential pair of signal line segments (). The pair of tuning line segments () is connected with its respective end terminals () to a common reference potential and further comprises a tunable element () arranged between a first portion () and a second portion () of the pair of tuning line segments () and configured to change the impedance of the pair of tuning line segments ().

Tunable differential transmission line segment

A calibration unit and method therein for calibrating a TDC comprised in a digital PLL are disclosed. The TDC receives a signal from a free-running DCO and a reference signal, and measures the time difference between the DCO and reference signals. The calibration unit receives and processes data samples output from the TDC and generates a calibration lookup table in which each TDC output value has a calibration value. The calibration lookup table may be used for post-distortion. For each TDC output level the corresponding calibration value from the lookup table may be added to the output of the TDC for correction.

Time to digital converter calibration

A frequency determination device for determining a frequency relationship between a reference signal and a clock signal. Each constituent TDC is configured to provide a digitally represented constituent output signal in response to receiving a constituent reference signal and a constituent clock signal, and the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal of a first constituent TDC as respective constituent clock signals to the other constituent TDC:s. The reference signal provider is configured to provide the respective constituent reference. The switching circuitry is configured to provide the reference signal as the constituent clock signal to the first constituent TDC. The determination circuitry is configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals of the constituent TDC:s, and to determine the frequency relationship.

Devices and method for frequency determination

A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.

Time to digital converter arrangement with increased detection range

A time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The TDC circuitry comprises multiple constituent TDCs, a reference signal provider, and a digital signal combiner. Each TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal. The reference signal provider is configured to provide the respective constituent reference signals to each of the TDCs. In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner is configured to provide the digitally represented output signal based on the digitally represented constituent output signals of the TDCs.

Time-to-digital converter circuitry

A technique for reading the columns () and rows () of a touch sensor () provides several advantages, including scalability to touch sensors with high column/row counts. A simultaneously applied set of column input signals () yields a corresponding set of column output signals () that are combined into a combined column signal () that is transformed into the frequency domain after digitization, to yield column values () corresponding to the respective touch sensor columns (). The same process applied with respect to the touch sensor rows () yields a set of row values (), with evaluation of the frequency-domain column and row values () providing the basis for detecting touch inputs to the touch sensor ().

A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal () and an input clock signal () to a digitally represented output signal (). The TDC circuitry comprises a plurality of constituent TDC:s (), a reference signal provider (), and a digital signal combiner (). Each constituent TDC is configured to convert a phase difference between a constituent reference signal () and a constituent clock signal () to a digitally represented constituent output signal (). The reference signal provider () is configured to provide the respective constituent reference signals () to each of the constituent TDC:s (). In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal () with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner () is configured to provide the digitally represented output signal () based on the digitally represented constituent output signals () of the constituent TDC:s. A corresponding method and devices comprising the TDC circuitry are also disclosed.

On-chip Multi-band equalizers for adjusting signal strength for a receiver receiving multi-band frequency signals are provided, The multi-band equalizer comprises multiple series connected tapped LC resonators. The tapped LC resonator may be capacitive tapping or inductive tapping, where both frequency and gain of the frequency bands of interest may be programmed by tuning the capacitances of the programmable capacitors and/or selecting the tapped out terminals of the inductors. The multi-band equalizer may be connected to a signal node, for instance between two amplifiers in the receiver.

Multi-band equalizers

An oscillator circuit () is disclosed. It comprises N amplifier circuits (A-A), connected in a ring and has a first and a second supply terminal (s, s). Each amplifier circuit (A-A) comprises an input transistor (M) having its gate connected to the input (in) of the amplifier circuit, its drain connected to an internal node (x) of the amplifier circuit, and its source connected to the first supply terminal (si). Furthermore, each amplifier circuit (A-A) comprises a first resonance circuit (R) comprising a first inductor (L) and a first capacitor (C), wherein the first inductor (L) is connected between the internal node (x) and the output (out) of the amplifier circuit, and the first capacitor (C) is connected between the output (out) of the amplifier circuit and one of the first and the second supply terminals (s, s). Moreover, each amplifier circuit (A-A) comprises a second resonance circuit (R) comprising a second inductor (L) and a second capacitor (C), wherein the second inductor (L) and the second capacitor (C) are connected in parallel between the internal node (x) and the second supply terminal (s).

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Göteborg, Sweden

Mohammed Abdulaziz