Intel Corporation

Mohammed A El-Tanani

Paul A Packan

Jad Rizk

Jami A Wiedemer

Andrey Mezhiba

Yonping Fan

A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.

CMOS varactor with increased tuning range

Techniques are disclosed for enhancing performance of integrated or on-chip inductors by implementing a schema of conductive metal dummies in the design thereof. In some cases, a metal dummy schema may be disposed in a layer proximate an upper surface of the inductor. The techniques may be implemented to improve overall inductor performance while enabling area scaling effects such as shrinking of inductor-to-inductor spacing on a die and/or increasing the quantity of inductors that may be manufactured on a die. In some cases, conductive metal dummies may be disposed in a region of minimal or non-peak magnetic field relative to the inductor, orthogonal to current flow in the inductor, and/or so as to minimize their occupation of the overall area of the inductor. The techniques may be implemented in analog circuits such as inductor-capacitor phase-locked loops (LC-PLLs), high-volume architectures, processor microarchitectures, applications involving stringent jitter requirements, microprocessor clocking, and wireless communication systems.

Growing community of inventors

Portland, OR, United States of America

Mohammed A El-Tanani