Synopsys, Inc.

Mohammad Ziaullah Khan

Deepak Dattatraya Sherlekar

Jovanka Ciric Vujkovic

Anand Arunachalam

Abhijeet Chakraborty

Van E Morgan

David John Seibert

Maurizio Damiani

Xinwei Zheng

Tsuwei Ku

Channakeshav Ananth

Xiaoyan Yang

Dongxiang Wu

Mayank Jain

Mustafa Kamal

Jeff Ku

Muniraj Ramamurthy

Linuo Xue

Guilherme Augusto Flach

A system expands an existing library based on simultaneous optimization of a circuit design being built and the library cells being used. The system receives a library of cells and a circuit design and performs synthesis and optimization of the circuit design. The system evaluates the circuit design to identify portions that may be candidates for new library cells. The system analyzes the library to determine whether there is an existing library cell that can be used, whether the new libcell should be added to the library, or whether the new libcell should replace an existing libcell. The system performs modeling for the new libcell to measure the improvement obtained by use of the new libcell. The system recommends the new libcell for addition to the library based on the performance modeling.

Library design and co-optimization with a circuit design

Embodiments herein describe a techniques for identifying a first combinational cellin a design for an integrated circuit, identifying a plurality of candidate combinational cellsto combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell. Upon determining the MB combinational cell satisfies a performance threshold, the first combinational cell and the at least one of the plurality of candidate combinational cells are replaced with the MB combinational cell in the design.

Integrated circuit design using multi-bit combinational cells

A method includes receiving a design file for a circuit design and receiving a library that defines a cell that includes one or more inputs, a first combinational logic circuit element, a second combinational logic circuit element, a first output, and a second output. The method also includes replacing a plurality of circuit elements in the circuit design with the cell and compiling the circuit design after replacing the plurality of circuit elements with the cell. The first and second outputs of the cell in the compiled circuit design replace a plurality of outputs of the plurality of circuit elements.

Construction, modeling, and mapping of multi-output cells

Refining multi-bit flip flops mapping without explicit de-banking and re-banking is provided by identifying a set of equivalent flops in a layout, that include a first flop having a first logic routing and a first location in the layout and a second flop having a second logic routing and a second location in the layout; and remapping the first logic of the first flop from the first location to the second location and the second logic of the second flop from the second location to the first location.

Refining multi-bit flip flops mapping without explicit de-banking and re-banking

Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level.

Method and apparatus for automatic relative placement rule generation

Growing community of inventors

Mountain View, CA, United States of America

Mohammad Ziaullah Khan