Texas Instruments Corporation

Intersil Corporation

Other

Integrated Sensor Solutions

Harris Corporation

Chrontel Inc.

Mohammad Yunus

Graham Y Mostyn

Charles Anthony Odegard

Ferdinand Borromeo Arabe

David Chee-Fai Soo

Anthony Louis Coyle

Tz-Cheng Chiu

Yiwei Wang

Sofjan Goenawan

Finbarr J Crispie

Jerald R Bernacchi

Peter W Cheng

Apparatus and associated methods relate to a system or method of precision battery charge measurement. Some embodiments may include precise charge and discharge control based on precision battery voltage and current sensing. In an illustrative example, energy either going in or out of the battery may be multiplied or computed using novel circuitry. In various embodiments, energy may be computed in a precision energy small unit determined as a percentage of total battery capacity. In an illustrative example, the precision unit may be, for example, 0.0018% of the total battery capacity. In some embodiments, the energy meter value may be in digital form, so it can be stored in memory and transmitted to external users as desired using USB type C or any other method. Various embodiments may advantageously provide extended battery life, based on using the measured energy meter value to maintain the state of charge of the battery.

Precision battery energy measuring system

Apparatus and associated methods relate to configuring a circuit to sense current in a low-cost non-precision resistance, calibrating the circuit to correct inaccuracy measured in the sensed current, and measuring with the corrected circuit the precise current sensed in the low-cost non-precision resistance. In an illustrative example, the low-cost non-precision resistance may be a metal trace on a printed circuit board. The circuit may be calibrated, for example, over a range of currents or temperatures, permitting automatic adjustment to a wide range of non-precision resistance parameter values and environmental conditions. In some examples, correcting coefficients may be adapted to compensate for resistance non-linearities, which may include skin effect or self-heating. Some embodiments may verify the calibrated correction over a range of current and temperature. Various examples may advantageously provide high precision measurement at reduced cost, based on calibrating a circuit to obtain corrected measurement sensed with a low-cost non-precision resistance.

Precision current sensing using low cost sense resistance

A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Patterned plasma treatment to improve distribution of underfill material

According to one embodiment of the invention, a method of packaging flip chips includes providing a plurality of flip chips and a panel, forming a plurality of partitions outwardly from the panel, coupling the flip chips to the panel such that each partition surrounds a respective flip chip, and forming an underfill region between each of the flip chips and the panel. Each partition prevents a respective underfill region from engaging an adjacent underfill region.

Method and system for flip chip packaging

A flip chip optoelectronic device assembly includes a hollow, cylindrical spacer between an optical source in the substrate and the active surface of the chip, which precludes attenuation of the signal and allows direct transmission through air. An underfill material fills the space between chip and substrate, thereby allowing substrates which are not necessarily matched in thermal expansion to the chips, and the spacer acts as a dam to prevent ingress of underfill material into the optical path. The spacer not only allows use of conventional underfill materials to support the interconnection joints and thermal mismatch, but also defines a fixed 'z' axis distance between substrate and chip.

Optical coupling for a flip chip optoelectronic assembly

Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a surface. Using a layer of polymeric material, the chip surface is mounted on the substrate surface. The polymeric material protrudes beyond the chip periphery and spreads some distance along the substrate surface. A metal layer is on the substrate surface, this layer is shaped as a band around the chip periphery; the band has an inner edge near the chip periphery, and an outer edge near the contour of the polymer protrusion. This metal band serves as a guard ring to stop any nascent crack propagating in the polymer protrusion.

Flip-chip device strengthened by substrate metal ring

A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Contact structure for reliable metallic interconnection

A method for testing a cell in a device for reliability is disclosed. The cell us coupled to a reference voltage and a current source. The method and system comprises measuring a mirrored current through the device at first predetermined gate voltage and measuring a mirrored current through the device at a second predetermined voltage. The method and system includes determining the threshold voltage of the cell and heating the device for a predetermined period of time. Finally, the method and system includes calculating a new threshold voltage if the measured mirrored current is different from the previously measured current. Accordingly, a system and method in accordance with the present invention addresses this drift problem by testing the characteristics of the memory array on a bit by bit basis. A system and method in accordance with the present invention includes a mirrored current source arrangement. The mirrored current source arrangement allows for the determination of the overall change in characteristic of the threshold voltage. In so doing, the device can be tested more accurately and quickly, thereby reducing the time for testing and increasing the reliability of the device.

Method and system for testing a bit cell in a memory array

A signal processing circuit is disclosed. The signal processing circuit comprises a sensor for receiving a voltage and providing a first signal based on at least one parameter. The signal processing circuit further includes a first digital to analog converter (DAC) for providing a supply voltage to the summer and a second DAC for providing a voltage (V.sub.tc) which is dependent upon the supply voltage and a variation in temperature of the supply voltage. The signal processing circuit also includes a summer coupled to the first and second DACs for receiving the first signal and providing a first output and a gain circuit for receiving the first output and providing an output voltage. In accordance with the system and method of the present invention, a voltage V.sub.tc which is dependent on the supply voltage and a variation in temperature of the supply voltage can be utilized advantageously to minimize the number of DACs in the signal processing system. This technique can be extended to do temperature correction of first order or higher order (for example, polynomial type of correction), or piece wise linear temperature correction. The main benefits of this technique are minimal hardware use and filtered digitized temperature steps in the signal processing. It can be extended to calibrate out errors due to other sensed signals if the primary sensed signal is affected by those other signals.

Signal processing circuit which provides for a temperature dependent

A method and system for providing a filter having an increased speed and decreased settling time are disclosed. The method and system comprise summing means for adding and subtracting. The method and system further comprise means coupled to the summer for providing a delay; and a clock coupled to the delay providing means. The clock determines a number of samples during a predetermined time. The clock is operated at a plurality of frequencies such that the total number of samples during the predetermined time is a predetermined number. According to the method and system disclosed, the filter has an increased speed. The increased speed of the filter can operate to extend the lifetime of power devices.

Method and system for a digital filter having improved settling time

A digital compensation circuit for calibrating a sensor is described. The compensator circuit includes a serial communication circuit for receiving data relating to a plurality of parameters and a compensation circuit coupled to serial communication circuit for providing piece-wise linear compensation of a temperature coefficient (TC). In one embodiment, the compensation circuit further includes a detector for detecting a threshold for a digital temperature and providing an output and a plurality of registers coupled to the detector and the serial communication circuit, a first plurality of registers for providing a first value if the digital temperature is above the threshold, a second of the plurality of registers for providing a second value if the digital temperature is below the threshold. The compensation circuit further includes a selector coupled to the detector and the plurality of registers for selecting one of the first and second of the plurality of registers dependent upon the output of the detector for providing piece-wise linear compensation of a temperature coefficient.

System and method for high accuracy calibration of a sensor for offset

A method and system for calibrating a sensor is disclosed The method and system include receiving data relating to a plurality of temperature parameters and providing polynomial compensation of a temperature coefficient (TC). When providing polynomial compensation of the temperature coefficient, the method and system further include providing a first output and adding a second value to the first output. The first output is a distal temperature multiplied by a first value.

System and method for precision compensation for the nonlinear offset

A circuit and method for avoiding latch up in an integrated circuit in which the base-emitter junction of a parasitic bipolar transistor forming part of a parasitic SCR structure is monitored. If the forward bias of the monitored base-emitter junction approaches a predetermined value, the operation of the circuit is altered to prevent activation of the SCR.

Structure and method for preventing latch-up in integrated circuits

A sigma-delta analog-to-digital converter employs multiplexed single-loop modulators in parallel and respectively phased time-divided clocks. The parallel modulators have the effect of producing digital output at a high sampling frequency that is a multiple of the phased switching frequencies applied to the modulator circuits. In one preferred embodiment, four second-order sigma-delta modulators are driven in clocked phased sequence and combined by a multiplexor circuit. Another embodiment employs second-order modulators using RC integrators. A further embodiment replaces the multiplexor with an adder when in-phase modulator clocks are used, and the adder also acts as a simple low pass filter.

Growing community of inventors

Dallas, TX, United States of America

Mohammad Yunus