Qualcomm Incorporated

Mohammad Tamjidi

Parag Arun Agashe

Hee Jun Park

Rajat Mittal

Madan Krishnappa

Rajit Chandra

Jeffrey Gemar

Matthew Levi Severson

Dipti Ranjan Pal

Ali Taha

Suresh Sugumar

Shih-Hsin Jason Hu

Harshat Pant

Hee-Jun Park

Amy Derbyshire

Tao Xue

Noman Ahmed

Mark Kempfert

Ramprasath Vilangudipitchai

Srijith Nair

An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.

Clock glitch prevention for retention operational mode

A thermal controller for managing thermal energy of a multi-core processor is provided. The cores include a first core processing a load and remaining cores. The thermal controller is configured to determine that a temperature of the first core is greater than a first threshold, determine a temperature of a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold, and determine whether the temperature of the second core is greater than or less than a second threshold. The thermal controller is configured to transfer at least a portion of the load of the first core to the second core in response to determining that the temperature of the first core is greater than the first threshold and based on whether the temperature of the second core is greater than or less than the second threshold.

Thermal mitigation of multi-core processor

An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Processor power management responsive to a sequence of an instruction stream

Various embodiments of methods and systems for dynamically adjusting a peak dynamic power threshold are disclosed. Advantageously, embodiments of the solution for peak dynamic power management optimize a peak dynamic power threshold based on estimations of real-time leakage current levels and/or actual power supply levels to a power domain of a system on a chip ('SoC'). In this way, embodiments of the solution ensure that a maximum amount of available power supply is allocated to dynamic power consumption for processing workloads at an optimum performance or quality of service ('QoS') level without risking that the total power consumption (leakage power consumption+dynamic power consumption) for the power domain exceeds the power supply capacity.

System and method for peak dynamic power management in a portable computing device

A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.

Token-based power-switch control circuits

A method, an apparatus, and a computer program product are provided. The apparatus may be a UE. The UE has a processor including a plurality of cores. The plurality of cores includes a first core and remaining cores. The UE determines a temperature of the first core of the plurality of cores. The first core processes a load. The UE determines that the temperature of the first core is greater than a first threshold. The UE determines that the temperature of the first core is not greater than a second threshold. The second threshold is greater than the first threshold. The UE transfers at least a portion of the load of the first core to a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold.

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San Diego, CA, United States of America

Mohammad Tamjidi