Inphi Corporation

Cirrus Logic Inc.

Mohammad Ranjbar

Jorge Pernillo

Bruce Eliot Duewer

Yousof Mortazavi

Arash Mashayekhi

The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

Systems and methods for comparator calibration

The present invention is directed to signal processing systems and methods thereof. In various embodiments, the present invention provides an analog-to-digital conversion (ADC) system that includes a flash ADC portion and a time-interleaved parallel SAR portion. For an n-bit ADC process, the flash ADC portion converts k MSBs of the n bits during a single cycle, and the SAR portion converts n&#x2212;k LSBs in m number of cycles. The SAR portion includes a number of SAR channels that perform A/D conversion in parallel, and the k MSB from the course flash converter is verified for errors by the SAR portion and allows a net saving of the power consumption by reducing the number of fine resolution SARs. There are other embodiments as well.

High-speed analog-to-digital conversion system with flash assisted parallel SAR architecture

In a switched-power amplifier that has controlled power supply rails, e.g., when a volume control is implemented by varying the power supply voltages, a rate-controlled power supply control circuit eliminates audible pops that would otherwise occur when a change in input level causes the power supply rail voltages to change. The control circuit generates control signals that control the regulators providing the power supply rails with a controlled rate of change such that asymmetry between the voltages of the power supply rail outputs during changes of the power supply rails is substantially reduced. The controlled rate of change is less than or equal to the slowest rate of change of the power supply outputs that supply the power supply rails of the switched-power amplifier.

Switching power amplifier with rate-controlled power supply voltage transitions

The stability of a delta-sigma modulator may be improved by limiting a value within the delta-sigma modulator. For example, the value provided to a quantizer may be limited, by a limiter circuit in the delta-sigma modulator, to a value within a single step range of the quantizer. The limiter circuit may be placed in an inner loop of the delta-sigma modulator to decouple the stability of the inner loop from an outer loop. For example, a delta-sigma modulator may be constructed with an inner loop having a sixth order and an outer loop having a second order, in which the stability of the delta-sigma modulator is proportional to that of a second order.

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San Jose, CA, United States of America

Mohammad Ranjbar