Xilinx, Inc.

Dolphin Technology, Inc.

Mohammad R Tamjidi

Jennifer Wong

Richard C Li

Hassan K Bazargan

Scott S Nance

An output driver that includes a waveform detector and a driver unit. The waveform detector receives at least one data signal, detects for particular patterns of interest (e.g., a sequence of zeros or ones) within the received data signal, and provides one or more control signals indicative of the detected patterns of interest. The driver unit receives the data signal and provides at least one output signal in response thereto. The driver unit further receives the control signal(s) and adjusts one or more characteristics of the output signal based on the received control signal(s). Various characteristics of the output signal (e.g., slew rate, delay, drive strength, and others) can be adjusted to achieved the desired result (e.g., reduced amount of skew, ISI). The driver unit can be designed to include a pre-driver that receives the data signal and provides at least one pre-drive signal and a driver that receives the pre-drive signal and provides the output signal. The pre-driver and drive can each further receive the control signal(s) and adjust one or more characteristics of its output signal based on the received control signal(s).

Waveform compensated output driver

A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. One embodiment of the present invention comprises a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit. The interface circuit provides a high impedance receive mode. In this mode, when a voltage is applied to the I/O pin of the interface circuit which is sufficiently greater than the interface circuit power supply voltage, the isolation circuit isolates the power supply from the I/O pin. The interface circuit also protects all of the transistors from gate to bulk, gate to source and gate to drain voltage drops of greater than a specified voltage, for example 3.6V for a nominal 3V power supply when up to 5.5V is being externally applied to the I/O pin. In high impedance mode when the externally applied voltage at the I/O pin is sufficiently below the interface circuit supply voltage, the isolation circuit is driven to approximately the interface circuit supply voltage. In low impedance mode the isolation circuitry is disabled and the logic level at the data terminal is transmitted to the I/O pin. One embodiment of the present invention provides a buffered data path from the data terminal to the I/O pin.

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Milpitas, CA, United States of America

Mohammad R Tamjidi