Freescale Semiconductor,inc.

Mohammad Nizam U Kabir

Douglas Alan Garrity

Brandt Braswell

Rakesh Shiwale

Steven P Allen

Ahmad H Atriss

Merit Y Hong

A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the first control node and a first current output node or between the second control node and a second current output node, and an activation current source provides activation current to the buffer circuit via the first and second control nodes. The master replica bias network replicates biasing of the buffer circuit relative to a replica control node and drives the buffer circuit to maintain the first control node, the second control node and the replica control node at a common master control voltage.

Digital to analog converter with current steering source for reduced glitch energy error

An analog-to-digital converter stage includes: a comparator and logic circuit having first upper and lower unscaled voltage trip points that are different than upper and lower residue voltage trip points; and a switched capacitor circuit. The comparator and logic circuit is configured prior to an initial residue calculation cycle to compare a magnitude of an unscaled input voltage to the first upper and lower unscaled voltage trip points, to generate an initial output bit, and to generate a voltage scaling and gain control signal. The switched capacitor circuit is configured to sample the unscaled input voltage, to receive a reference voltage, and to receive the voltage scaling and gain control signal for selectively controlling a subset of switches of the switched capacitor circuit to scale the unscaled input voltage sample and reference voltage and generate an initial residue voltage during a single operation of the initial residue calculation cycle.

Analog to digital conversion architecture and method with input and reference voltage scaling

A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.

A sampling switch circuit uses correlated level shifting. The sampling switch circuit includes: a sampling switch having a first terminal, a control terminal, and an output terminal, wherein the first terminal is connected to an input voltage node; a boosting circuit connected to first and second supply voltage nodes and coupled to the control terminal of the sampling switch; and a correlated level shifting buffer circuit. The correlated level shifting buffer circuit includes: an amplifier having first and second inputs and an output, wherein the first input is connected to the input voltage node, and the output and second input are coupled to the boosting circuit; and a level shifting capacitor coupled to the second input and output of the amplifier, to the boosting circuit, and to a level shifting voltage node.

Sampling switch circuit that uses correlated level shifting

A sample and hold circuit is provided. The circuit includes a plurality of switches, a first capacitor, an operational amplifier having a first input selectively coupled to the first capacitor and an output, a second capacitor and a third capacitor both selectively coupled to the first capacitor and both selectively coupled between the first input of the operational amplifier and the output of the operational amplifier, wherein the plurality of switches are configured to receive a plurality of control signals such that the first capacitor is configured to sample an input signal in a sample phase and to transfer a charge to one of the second capacitor and the third capacitor in a hold phase, and the second capacitor and third capacitor are configured to alternate between holding the transferred charge and resetting in any back-to-back hold phases.

Sample and hold circuit

A comparator is provided. In one embodiment, a method of operating a comparator comprises providing a bias current (); comparing an input signal and a reference signal to determine a difference signal and an inverted difference signal (); latching the difference signal and the inverted difference signal to generate a first and second latched signals (); generating a control signal using at least the first and second latched signals (); and controlling the bias current in response to the control signal (), wherein the comparing the input signal and the reference signal () is activated and deactivated in response to the controlling the bias current (). In another embodiment, a comparator comprises a bias circuit () configured to provide a bias current; a comparator circuit () configured to determine a difference signal and an inverted difference signal by comparing an input signal and a reference signal, wherein the bias current is used to place the comparator circuit () in an active mode; a latch circuit () configured to latch the difference signal and the inverted difference signal to generate a first and second latched signals; a control circuit () configured to generate a control signal using at least the first and second latched signals; and a switch circuit () configured to use the control signal to control the bias current to place the comparator circuit () in an active mode and an inactive mode.

Comparator

An analog to digital converter includes a first sample circuit that samples an analog input during a first phase of a clock. A second sample circuit samples the analog input during a second phase of the clock. A comparator compares a reference to the output of the first sample circuit during a non-overlapping time between an end of the first phase and beginning of the second phase and compares the reference to the output of the second sample circuit during a non-overlapping time between an end of the second phase and beginning of the first phase. The first sample circuit couples the sample of the analog input taken by the first sample circuit to the input of the comparator during the non-overlapping time between the end of the first phase and the beginning of the second phase and the second sample circuit couples the sample of the analog input taken by the second sample circuit to the input of the comparator during the non-overlapping time between the end of the second phase and the beginning of the first phase.

Analog-to-digital converter having a comparator for a multi-stage sampling circuit and method therefor

A converter () adapted to convert an analog input signal into a digital output signal includes an analog input terminal () for receiving the analog input signal, a Redundant Signed Digit (RSD) stage () coupled to the analog input terminal, and a digital section (). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.

Current reduction in a single stage cyclic analog to digital converter with variable resolution

Embodiments include integrator systems, switched-capacitor circuits, and methods of their operation. An integrator system comprises a differential amplifier and first and second sampling modules. The first sampling module includes a first capacitor and a first set of switches. The first set of switches changes a connection status between the first capacitor and first and second amplifier input terminals when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and refrains from changing the connection status when the change in the polarity does occur. The second sampling module includes a second capacitor and a second set of switches. The second set of switches changes a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity does occur, and refrains from changing the connection status when the change in the polarity does not occur.

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Tempe, AZ, United States of America

Mohammad Nizam U Kabir