Broadcom Corporation

Mohammad Nejad

Guangming Yin

Jun Cao

Ali Ghiasi

Bo Zhang

Daniel Schoch

Sridevi R Joshi

Ichiro Fujimori

Rajagopal Anantha Rao

Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Symmetrical clock distribution in multi-stage high speed data conversion circuits

A bit stream multiplexer and a bit stream demultiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream demultiplexer includes similar demultiplexing integrated circuits. These circuits include an interface that may be ordered, have signal line polarities altered, or bit asserted states altered depending upon the particular implementation.

Signal line selection and polarity change of natural bit ordering in high-speed serial bit stream multiplexing and demultiplexing integrated circuits

A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Source centered clock supporting quad 10 GBPS serial interface

Apparatus and method are disclosed for constructing an eye pattern from a serial data signal within a receiver used in a serial data communication system. The receiver is used to receive the serial data signal and generates an internal clock signal from the serial data signal using, at least in part, a CDR circuit. Timing data corresponding to a current phase of the clock signal is also generated within the receiver using an interpolator circuit. The serial data signal is sampled by an ADC using the clock signal to generate sampled data. The sampled data and timing data are processed within the receiver by a data processor to generate the eye pattern. The resultant eye pattern may be analyzed within the receiver with respect to at least one characteristic of the eye pattern. At least one parameter of the receiver may be adjusted in response to the foregoing analysis.

Eye monitoring and reconstruction using CDR and sub-sampling ADC

A multi-stage bit stream multiplexer that divides multiplexing functions between two or more integrated circuits. The first integrated circuit receives 16 bit streams to produce 4 output bits streams with a nominal data rate of 10 GBPS. A second integrated circuit multiplexes the 4 streams and to a bit stream with a data rate of 40 GBPS. The first IC is made in a standard CMOS process while the second IC is made using processes that support higher switching rates. The first IC produces a source-centered double data rate forward transmit clock from a reference clock selectable from either a crystal oscillator, a voltage controlled oscillator using a loop clock from the receive side of the bit stream multiplexer or a reverse clock generated by the second IC. The reverse clock can be selected as the source of the reference either by default, or in response to a specific condition.

Multi-stage multiplexing chip set having switchable forward/reverse clock relationship

A bit stream demultiplexer that couples a high-speed bit stream media to a communication Application Specific Integrated Circuit (ASIC). The bit stream multiplexer performs its demultiplexing function staged within at least two integrated circuits. The first Integrated Circuit (IC) receives a first bit stream and performs a first demultiplexing function. A second IC performs a second demultiplexing function. The second IC acts as either a slave or a master to the first IC. In a slave mode, the second IC depends upon a transmit data clock from the first IC for latching bit stream data received from the first IC. When the second IC operates in the master mode, the second IC uses the transmit data clock from first IC as a reference input for a PLL to generate a Receive Data Clock. If an LOL or LOS occurs within the first IC, a signal to the second IC indicates these conditions causing the second IC to switch to a local oscillator reference clock to generate the Receive Data Clock.

Multi-stage high speed bit stream demultiplexer chip set having switchable master/slave relationship

A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate and in a natural order. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

High-speed serial bit stream multiplexing and demultiplexing integrated circuits

The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

An integrated circuit includes a core circuit and a buffer circuit. The buffer circuit includes a plurality of input buffers and a plurality of output buffers that service a plurality of voltage domains on a single set of input/output lines. These voltage domains are controllable to service multiple voltage levels, consistent with various interface standards. In one construction, the core circuit operates at 1.2 volts and the buffer circuit supports both a 1.2 volts interface standard and a 3.3 volts interface standard.

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Newport Beach, CA, United States of America

Mohammad Nejad