Qualcomm Incorporated

Mohammad Meysam Zargham

Yan Wang

Dinesh Jagannath Alladi

Masoud Roham

Li Lu

Liang Dai

Elias Dagher

Mohammad Ghasemazar

Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.

Successive approximation register analog-to-digital converter chopping

Apparatuses are presented. The apparatus includes a sensor configured with an adjustable accuracy setting to measure a physical parameter and a controller configured to adjust the accuracy setting based on a threshold, and to adjust the threshold based on the physical parameter measured by the sensor. Another apparatus includes a sensor configured with a plurality of sensor accuracy settings to measure a physical parameter of a circuit in a plurality of operating regions. The plurality of operating regions is based on ranges of the physical parameter measured by the sensor. Each of the plurality of sensor accuracy settings corresponds to one of the plurality of operating regions. A controller is configured to adjust one of the ranges of the physical parameter for one of the plurality of operating regions, in response to a change of an operating condition of the circuit.

Dynamic sensor accuracy setting threshold

Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

Continuous-time delta-sigma ADC with scalable sampling rates and excess loop delay compensation

Certain aspects of the present disclosure provide methods and apparatus (e.g., a level shifter) for buffering an oscillating signal generated by an oscillator. One example apparatus generally includes an amplifier having a first amplification stage configured to amplify the oscillating signal generated by the oscillator and a second amplification stage configured to amplify an inverse of the oscillating signal generated by the oscillator; and a sensing circuit configured to adjust an operational bandwidth of the amplifier based on a frequency of the oscillating signal.

Wide frequency/voltage-ratio buffer with adaptive power consumption

A device and method for analog to digital conversion is disclosed. The device can have a first amplifier operable to receive an input voltage and output a first control signal. The device can also have a first voltage-controlled oscillator (VCO) operably coupled to the first amplifier and configured to output a first signal based on the first control signal, the first signal having a sensor frequency. The device can also have a first switched-capacitor resistor operably coupled to the first VCO and to the first amplifier, the first switched-capacitor resistor configured to receive and be controlled by the sensor frequency. The device can also have a sensor counter operably coupled to the first VCO and configured produce a sensor count based on the sensor frequency. The device can also have a register configured provide a digital output proportional to the input voltage based on the sensor count.

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San Diego, CA, United States of America

Mohammad Meysam Zargham