Applied Materials, Inc.

Mohammad Kamruzzaman Chowdhury

Ajay Kumar

Wei-Sheng Lei

Brad Eaton

Nag B Patibandla

Todd J Egan

Mingwei Zhu

Yong Cao

Zhebo Chen

Madhava Rao Yalamanchili

Zihao Yang

Shane Lavan

Shriram Mangipudi

Edwin C Suarez

Abhishek Chowdhury

Arun Chakravarthy Chakravarthy

Nataraj Bhaskar Rao

Harisha Sathyanarayana

Diego Ramiro Puente Sotomayor

Qanit Takmeel

Adolph Miller Allen

Zhenbin Ge

Deposition ring of a process kit for semiconductor substrate processing

Grounding ring of a process kit for semiconductor substrate processing

A superconducting device includes a substrate, a metal oxide or metal oxynitride seed layer on the substrate, and a metal nitride superconductive layer disposed directly on the seed layer. The seed layer is an oxide or oxynitride of a first metal, and the superconductive layer is a nitride of a different second metal.

High critical temperature metal nitride layer with oxide or oxynitride seed layer

A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate, exposing the seed layer to an oxygen-containing gas or plasma to form a modified seed layer, and after exposing the seed layer to the oxygen-containing gas or plasma depositing a metal nitride superconductive layer directly on the modified seed layer. The seed layer is a nitride of a first metal, and the superconductive layer is a nitride of a different second metal.

Method of making high critical temperature metal nitride layer

A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate at a first temperature, the seed layer being a nitride of a first metal, reducing the temperature of the substrate to a second temperature that is lower than the first temperature, increasing the temperature of the substrate to a third temperature that is higher than the first temperature to form a modified seed layer, and depositing a metal nitride superconductive layer directly on the modified seed layer at the third temperature, the superconductive layer being a nitride of a different second metal.

A method of processing a substrate includes: sputtering target material for a first amount of time using a first plasma formed from an inert gas and a first amount of power; determining a first counter, based on a product of a flow rate of the inert gas, the first amount of power, and the first amount of time; sputtering a metal compound material for a second amount of time using a second plasma formed from a process gas comprising a reactive gas and an inert gas and a second amount of power; determining a second counter based on a product of a flow rate of the process gas, the second amount of power, and the second amount of time; determining a third counter; and depositing a metal compound layer onto a predetermined number of substrates, wherein a deposition time for each substrate is adjusted based on the third counter.

Counter based time compensation to reduce process shifting in reactive magnetron sputtering reactor

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.

Etch-resistant water soluble mask for hybrid wafer dicing using laser scribing and plasma etch

Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.

Multi-layer mask including non-photodefinable laser energy absorbing layer for substrate dicing by laser and plasma etch

Methods and systems of laser and plasma etch wafer dicing using UV-curable adhesive films. A method includes forming a mask covering ICs formed on the wafer. The semiconductor wafer is coupled to a film frame by a UV-curable adhesive film. A pre-cure of the UV-curable adhesive film cures a peripheral portion of the adhesive extending beyond an edge of the wafer to improve the exposed adhesive material's resistance to plasma etch and reduce hydrocarbon redeposition within the etch chamber. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the ICs. A center portion of the UV-curable adhesive is then cured and the singulated ICs detached from the film.

Laser and plasma etch wafer dicing with partial pre-curing of UV release dicing tape for film frame wafer application

Uniform masking for wafer dicing using laser and plasma etch is described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits having bumps or pillars includes uniformly spinning on a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Uniform masking for wafer dicing using laser and plasma etch

Laser and plasma etch wafer dicing using UV-curable adhesive films. A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a carrier substrate by a double-sided UV-curable adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the ICs. The UV-curable adhesive film is partially cured by UV irradiation through the carrier. The singulated ICs are then detached from the partially cured adhesive film still attached to the carrier substrate, for example individually by a pick and place machine. The UV-curable adhesive film may then be further cured for the film's complete removal from the carrier substrate.

Laser and plasma etch wafer dicing with a double sided UV-curable adhesive film

Laser and plasma etch wafer dicing using UV-curable adhesive films is described. In an example, a method includes forming a mask above the semiconductor wafer. The semiconductor wafer is coupled to a carrier substrate by a UV-curable adhesive film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The UV-curable adhesive film is then irradiated with ultra-violet (UV) light. The singulated integrated circuits are then detached from the carrier substrate.

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Santa Clara, CA, United States of America

Mohammad Kamruzzaman Chowdhury