Innovium, Inc.

Broadcom Corporation

Tellabs San Jose, Inc.

Oracle America, Inc.

Mohammad Kamel Issa

Avinash Gyanendra Mani

Ajit Kumar Jain

Neil Barrett

William Brad Matthews

Bruce Hui Kwan

Ashwin Alapati

Mark David Griswold

Puneet Agarwal

Adam Julian Goldstein

Mitri Halabi

Amir Lehavot

Keith Michael Ring

Raghavan Menon

Shaham Parvin

Xiaoyang Zheng

Wael William Diab

Mohan V Kalkunte

David R Cheriton

Aly E Orady

Weihuang Wang

Shimon Muller

Ariel Hendel

Andreas V Bechtolsheim

Michael K Wong

Chien-Hsien Wu

Yatin Gajjar

Mani Kumaran

Srinivas Gangam

Gururaj Ananthateerta

Patrick James Bourke

Michael John Filardo

Raju Penumatcha

Anurag Kumar Jain

Approaches, techniques, and mechanisms are disclosed for efficiently buffering data units within a network device. A traffic manager or other network device component receives Transport Data Units ('TDUs'), which are sub-portions of Protocol Data Units (“PDUs”). Rather than buffer an entire TDU together, the component divides the TDU into multiple Storage Data Units (“SDUs”) that can fit in SDU buffer entries within physical memory banks. A TDU-to-SDU Mapping (“TSM”) memory stores TSM lists that indicate which SDU entries store SDUs for a given TDU. Physical memory banks in which the SDUs are stored may be grouped together into logical SDU banks that are accessed together as if a single bank. The TSM memory may include a number of distinct TSM banks, with each logical SDU bank having a corresponding TSM bank. Techniques for maintaining inter-packet and intra-packet linking data compatible with such buffers are also disclosed.

Efficient buffer utilization for network data units

Power demands of a computing system, such as a network device and/or a component thereof, are stabilized by introducing a programmable delay into identical or substantially similar subsystems within an integrated circuit. Each subsystem reads a potentially different delay value from an associated storage, memory, or input, and waits for some time indicated by the delay value before beginning execution. For example, in a group of identical subsystems that process data concurrently, some or all of the subsystems begin processing their respective data after a different amount of delay, thus staggering their respective executions and lowering the risk of aligned edges when some or all of the subsystems concurrently step their power demands up or down. This, in turn, reduces peak power and voltage. In an embodiment, rather than being fixed at the design stage, each subsystem's delay value is programmable at some point after fabrication.

Programmable delay-based power stabilization

Network chip utility is improved using multi-core architectures with auxiliary wiring between cores to permit cores to utilize components from otherwise inactive cores. The architectures permit, among other advantages, the re-purposing of functional components that reside in defective or otherwise non-functional cores. For instance, a four-core network chip with certain defects in three or even four cores could still, through operation of the techniques described herein, be utilized in a two or even three-core capacity. In an embodiment, the auxiliary wiring may be used to redirect data from a Serializer/Deserializer ('SerDes') block of a first core to packet-switching logic on a second core, and vice-versa. In an embodiment, the auxiliary wiring may be utilized to circumvent defective components in the packet-switching logic itself. In an embodiment, a core may utilize buffer memories, forwarding tables, or other resources from other cores instead of or in addition to its own.

Network chip yield improvement architectures and techniques

Approaches, techniques, and mechanisms are disclosed for efficiently buffering data units within a network device. A traffic manager or other network device component receives Transport Data Units ('TDUs'), which are sub-portions of Protocol Data Units ('PDUs'). Rather than buffer an entire TDU together, the component divides the TDU into multiple Storage Data Units (&#x201c;SDUs&#x201d;) that can fit in SDU buffer entries within physical memory banks. A TDU-to-SDU Mapping (&#x201c;TSM&#x201d;) memory stores TSM lists that indicate which SDU entries store SDUs for a given TDU. Physical memory banks in which the SDUs are stored may be grouped together into logical SDU banks that are accessed together as if a single bank. The TSM memory may include a number of distinct TSM banks, with each logical SDU bank having a corresponding TSM bank. Techniques for maintaining inter-packet and intra-packet linking data compatible with such buffers are also disclosed.

According to an embodiment, power demands of a computing device or component thereof may be stabilized by performing redundant operations during periods of otherwise low power demand. In so doing, the current load of the device/component remains relatively stable, potentially greatly reducing voltage droops and overshoots. This can reduce the peak voltage and peak power rating of the device/component. In certain embodiments, such as in network switches and routers, the redundant operations may include queries against a content addressable memory (CAM), such as a ternary content addressable memory (TCAM). Moreover, in an embodiment the queries may be designed to always, or at least be highly likely to, miss the entries in the CAM, thereby ensuring maximum power usage. In another embodiment, the redundant operations include read operations on a random access memory (RAM). In other embodiments, redundant operations may be performed with respect to other power-intensive subsystems.

Memory-based power stabilization in a network device

The technology described in this document can be embodied in an integrated circuit device comprises a first data processing unit comprising one or more input ports for receiving incoming data, one or more inter-unit data links that couple the first data processing unit to one or more other data processing units, a first ingress management module connected to the one or more inter-unit data links, the first ingress management module configured to store the incoming data, and forward the stored data to the one or more inter-unit data links as multiple data packets, and a first ingress processing module. The integrated circuit device also comprises a second data processing unit comprising one or more output ports for transmitting outgoing data, and a second ingress management module connected to the one or more inter-unit data links.

High-throughput multi-node integrated circuits

Ingress packet processors in a device receive network packets from ingress ports. A crossbar in the device receives, from the ingress packet processors, packet data of the packets and transmits information about the packet data to a plurality of traffic managers in the device. Each traffic manager computes a total amount of packet data to be written to buffers across the plurality of traffic managers, where each traffic manager manages one or more buffers that store packet data. Each traffic manager compares the total amount of packet data to one or more threshold values. Upon determining that the total amount of packet data is equal to or greater than a threshold value, each traffic manager drops a portion of the packet data, and writes a remaining portion of the packet data to the buffers managed by the traffic manager.

Reducing power consumption in an electronic device

Approaches, techniques, and mechanisms are disclosed for reutilizing discarded link data in a buffer space for buffering data units in a network device. Rather than wasting resources on garbage collection of such link data when a data unit is dropped, the link data is used as a free list that indicates buffer entries in which new data may be stored. In an embodiment, operations of the buffer may further be enhanced by re-using the discarded link data as link data for a new data unit. The link data for a formerly buffered data unit may be assigned exclusively to a new data unit, which uses the discarded link data to determine where to store its constituent data. As a consequence, the discarded link data actually serves as valid link data for the new data unit, and new link data need not be generated for the new data unit.

Instantaneous garbage collection of network data units

An improved buffer for networking devices and other computing devices comprises multiple memory instances, each having a distinct set of entries. Transport data units ('TDUs') are divided into storage data units ('SDUs'), and each SDU is stored within a separate entry of a separate memory instance in a logical bank. A grid of the memory instances is organized into overlapping horizontal logical banks and vertical logical banks. A memory instance may be shared between horizontal and vertical logical banks. When overlapping logical banks are accessed concurrently, the memory instance that they share may be inaccessible to one of the logical banks. Accordingly, when writing a TDU, a parity SDU may be generated for the TDU and also stored within its logical bank. The TDU's content within the shared memory instance may then be reconstructed from the parity SDU without having to read the shared memory instance.

Shared buffer memory architecture

Methods, systems, and apparatus, including a managed device comprising memory storage, one or more control registers, and circuitry to perform operations of receiving, from a control system, one or more posted write operations directed to the one or more control registers; based on the one or more posted write operations, storing in the one or more control registers, data specifying at least a system address of a memory of the control system, where the system address corresponds to a starting address of a predetermined section of the memory; and transferring managed device data from the memory storage to the predetermined section of the memory of the control system by issuing, to the control system and based on the system address of the memory, one or more posted write operations to write the managed device data to the predetermined section of the memory.

Posted operation data control

A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a link memory that is configured to maintain one or more pointers to interconnect the one or more data elements stored in the main memory. The memory system also includes a free-entry manager that is configured to generate an available bank set including one or more locations in the link memory. In addition, the memory system includes a context manager that is configured to maintain metadata for a list of the one or more data elements.

System and method for enabling high read rates to data element lists

Methods and apparatus for transmit buffers for network devices. One apparatus includes a packing unit, a buffer manager and a plurality of aggregated port buffers, each coupled to receive output from the packing unit. The packing unit is configured to receive packet data as input segments of a first size; generate storage units of a second size; and write each storage unit to a particular aggregated port buffer identified by the buffer manager. The buffer manager is configured to: select a particular aggregated port buffer for each storage unit, and send information to the buffer manager about the selected particular aggregated port buffer; monitor availability of storage space in the aggregated port buffers; control reception of input segments based on storage space availability; and manage transmission of the storage units from the aggregated port buffers to one or more external destinations as output segments of a third size.

Transmit buffer device for operations using asymmetric data widths

A memory system for a network device is described. The memory system includes a packing data buffer including a plurality of memory banks arranged in a plurality of rows and a plurality of columns. The packing data buffer is configured to store incoming data elements of a plurality of widths in the plurality of memory banks. The memory system also includes a free address manager configured to generate an available bank set based on one or more free memory banks in the plurality of memory banks. And, the memory system includes distributed link memory configured to maintain one or more pointers to interconnect a set of one or more memory locations of the one or more memory banks in the packing data buffer to generate at least one list.

Growing community of inventors

Los Altos, CA, United States of America

Mohammad Kamel Issa