Rambus Inc.

Samsung Display Co., Ltd.

Mohammad Hekmat

Amir Amirkhany

Dinesh D Patil

Reza Navid

Suresh Rajan

Farshid Aryanfar

Frederick Abbott Ware

Masum Hossain

Kambiz Kaviani

Jalil Kamali

Anup P Jose

Valentin Abramzon

Da Wei

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Semiconductor memory systems with on-die data buffering

A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

Method and apparatus for duty-cycle correction in a serial data transmitter

A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.

Digital calibration for multiphase oscillators

A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Hybrid half/quarter-rate DFE

An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.

Low overhead on chip scope

Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.

Integrated circuit comprising fractional clock multiplication circuitry

A display interface for transmitting reverse data. The display interface includes a timing controller, a first plurality of driver integrated circuits, a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits, and a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits. Each of the first plurality of driver integrated circuits has a data input configured to receive reverse data from a display panel, and a buffer configured to store reverse data. The timing controller is configured to periodically send a synchronization pulse having a triggering edge. Each of the first plurality of driver integrated circuits is configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.

Shared multipoint reverse link for bidirectional communication in displays

A method of calibrating coefficients of a calibrated decision feedback equalizer (DFE) across a process, voltage, and temperature (PVT) range, the calibrated DFE comprising a plurality of DFE taps for reducing distortions of an input signal, and a sampler for sampling the input signal, the method including applying a preset voltage to an input of the calibrated DFE, setting a DFE tap of the plurality of DFE taps to a maximum value, generating a source reference, via a source reference calibrator, to apply to the DFE tap, changing the source reference to a first level that causes an output of the sampler to transition from a first state to a second state, determining the first level as a calibrated source reference, and applying the calibrated source reference to the DFE tap during normal operation of the calibrated DFE.

Growing community of inventors

Mountain View, CA, United States of America

Mohammad Hekmat