Intel Corporation

Mohammad Ashraf Bhuiyan

Elmoustapha Ould-Ahmed-Vall

Eriko Nurvitadhi

Amit Bleiweiss

Deborah T Marr

Jeffrey J Cook

Srinivas Sridharan

Asit K Mishra

Dheevatsa Mudigere

Dhawal Srivastava

Anavai Ramesh

Md Faijul Amin

Niharika Maheshwari

Wei W Wang

Wei D Wang

Wei Wang

Brian R Nickerson

An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.

Machine learning accelerator mechanism

A decode unit to decode an instruction that indicates a source packed data that includes data elements, and indicates a source mask that includes mask elements. Each of the mask elements corresponds to a different one of the data elements. Each of the mask elements is one of a masked mask element and an unmasked mask element. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result packed data. When the source packed data includes one or more masked data elements disposed within unmasked data elements, the result packed data includes, the unmasked data elements consolidated together without the one or more masked data elements disposed within them. The execution unit, is to store a result in a second destination storage location that reflects a number of the unmasked data elements consolidated together.

Processors, methods, systems, and instructions to consolidate data elements and generate index updates

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Beaverton, OR, United States of America

Mohammad Ashraf Bhuiyan