Wayne State University

Mohammad Alhawari

Mohammed Ismail Elnaggar

Melvin D Edwards, Ii

Nabil Sarhan

Hamza Al-Maharmeh

A spatially unrolled time domain (TD) architecture that includes an input and weight register having i inputs and j weights, where i corresponds with a number of delay lines for i neurons, and j corresponds with a number of processing elements (PEs) for each delay line of the i delay lines. An enable control register sends a global input pulse to i neurons, and each delay line of the i delay lines includes the corresponding j PEs for that delay line. Each PE includes a digital-to-time converter (DTC) that accepts a digital input and weight and generates a relative delay, each time delay within a given delay line contributing to an overall delay for the given delay line. i time-to-digital converters (TDCs). A readout register receives digital outputs from each of the i TDCs, and serially outputs a signal from each of the i delay lines based on the overall time delay for each of the i delay lines.

Energy efficient digital to time converter (DTC) for edge computing

A ring oscillator includes a first set of at least three laddered inverter quantizer (LIQAF) circuits connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input creates a pair of phase shifted waveforms in the first of the at least three LIQAF circuits that propagate sequentially through the stages of the at least three LIQAF circuits. Each stage has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage.

Growing community of inventors

Dearborn, MI, United States of America

Mohammad Alhawari