Texas Instruments Corporation

Mohammad A Al-Shyoukh

Devrim Yilmaz Aksin

Eric Christian Blackall

Marcus Marchesi Martins

Alexander Noam Teutsch

Ayman A Fayed

Raul Alejandro Perez

Narasimhan R Trichy

David Hernandez-Garduno

Nicole Cunningham

Dircere Martins, Legal Representative

One embodiment of the invention includes a regulator circuit that regulates a substantially constant magnitude of an output voltage at an output node. The circuit includes a master stage configured to set a first threshold voltage and a second threshold voltage. The first threshold voltage can have a magnitude that is greater than the second threshold voltage. The circuit also includes a charging follower stage configured to conduct a first current from a first power rail to the output node. The first current can increase in response to a transient decrease of the output voltage relative to the first threshold voltage. The circuit further includes a discharging follower stage configured to conduct a second current from the output node to a second power rail. The second current can increase in response to a transient increase of the output voltage relative to the second threshold voltage.

Voltage regulator circuit

Multistage charge pumps with diode loss compensation are disclosed. In one example, a pre-regulated charge pump to generate a voltage is described. The example pre-regulated charge pump includes a charge pump having a plurality of stages and one or more diodes. The stages are configured to generate an output voltage at an output terminal based on an input voltage and a number of the multiplier stages. The example pre-regulated charge pump also includes a pre-regulator stage configured to adjust the input voltage to remove dependency on supply voltage variation. The pre-regulator includes a feedback diode configured to compensate for one or more voltage drops associated with the one or more charge pump diodes.

Multistage charge pumps with diode loss compensation

One embodiment of the invention includes a level-shifter circuit. The circuit comprises a control stage that steers a current from one of a first control node and a second control node to the other of the first control node and the second control node based on an input signal to set a first initial voltage at the first control node and a second initial voltage at the second control node, the input signal having logic-high and logic-low voltage magnitudes that occupy a low voltage domain. The circuit also includes a logic driver that is coupled to the second control node and is referenced in a high voltage domain. The logic driver can be configured to provide an output signal having logic-high and logic-low voltage magnitudes that occupy the high voltage domain based on the second initial voltage.

Level-shifter circuit

Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with the voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.

Fault protection circuit, method of operating a fault protection circuit and a voltage regulator employing the same

A real time clock (RTC) voltage regulator, a method of regulating an RTC voltage and a power management integrated circuit (PMIC). In one embodiment, an RTC voltage regulator includes a current source configured to provide a first current and a voltage regulator having a common gate amplifier and a power device. The first current is employed to establish a reference voltage for the common gate amplifier and the common gate amplifier is configured to control the power device. The power device is configured to provide an RTC voltage for the common gate amplifier.

Real time clock (RTC) voltage regulator and method of regulating an RTC voltage

One embodiment of the present invention includes a system for providing a soft-start for a power regulator comprising a differential transistor pair that receives an input current and conducts a first current through a first transistor and a second current through a second transistor. One of the first and second current changes in response to a change in the other to maintain a sum of the first and second current being substantially equal to the input current. The system also comprises a comparator that provides an output signal based on a comparison of a first input voltage and a second input voltage associated with the first current and the second current, respectively. The system further comprises a current source activated by the output signal to charge a capacitor that increases a soft-start reference voltage associated with control of the power regulator and which controls the change in the other of the first and second current.

Soft-start circuit for power regulators

Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with programmable hysteresis. Such circuits include a comparator input circuit that receives two inputs to be compared. The comparator input circuit provides a first differential current output based at least in part on a difference between the first voltage input and the second voltage input. The aforementioned circuits further include a hysteresis control circuit that is operable to receive a single programmable voltage input, and to provide a second differential current output based at least in part on the comparator output and the single programmable voltage input. An output circuit is also included that sums the first differential current and the second differential current, and provides a comparator output based at least in part on the sum of the first differential current and the second differential current.

Systems and methods for hysteresis control in a comparator

Systems and methods are provided for providing precision timing signals. A first register bank, driven by a first clock signal, provides a first delay along a first signal path. A second register bank, driven by a second clock signal related to the first clock signal, provides a second delay along a second signal path. A system control controls at least one of the first and second banks of registers to control the first and second delays, as to provide a desired skew between the output of the first signal path and the second signal path.

System and method for producing precision timing signals by controlling register banks to provide a phase difference between two signal paths

A low drop-out voltage regulator having soft-start. A low drop-out regulator circuit is provided having an input node, an output node, a power FET connected by a source and drain between the input node and the output node, and a feedback circuit having an output connected and providing a control signal to a gate of the power FET. A current limit circuit is configured to control the power FET to limit the current through it when the voltage across a controllable sense resistor connected to conduct a current representing the current through the power FET exceeds a predetermined limit value. At start-up, control unit provides a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease incrementally in value at respective predetermined incremental times during a predetermined time interval.

Soft-start circuit and method for low-dropout voltage regulators

A bootstrapped circuit for sampling inputs with a signal range greater than supply voltage includes: a bootstrapped switch coupled between an input node and an output node; a first transistor coupled to a control node of the bootstrapped switch; a first capacitor having a first end coupled to the first transistor; a second transistor coupled between the first transistor and a supply node, and having a control node coupled to a first clock signal node; a third transistor coupled between the first transistor and the supply node; a charge pump having an output coupled to a control node of the third transistor; a level shifter coupled to a second end of the first capacitor; a fourth transistor coupled between the supply node and a control node of the first transistor; and a fifth transistor coupled between the control node of the fourth transistor and the output of the charge pump and, having a control node coupled to the supply node; wherein the second end of the first capacitor can be charged to an input voltage.

Bootstrapped switch for sampling inputs with a signal range greater than supply voltage

A differential signal receiver and method is disclosed. One embodiment relates to a receiver for receiving a differential signal. The receiver includes a first voltage-to-current converter that converts the voltage received at a first input to a first current, and a second voltage-to-current converter that converts a voltage signal received at a second input to a second current. A current subtractor provides a difference current of the first and second currents that is indicative of the differential signal.

Differential signal receiver and method

The bootstrapping circuit capable of sampling inputs beyond supply voltage includes: a bootstrapped switch MNcoupled between an input node and an output node; a first transistor MPhaving a first end coupled to a control node of the bootstrapped switch MNa clock bootstrapped capacitor Chaving a first end coupled to a second end of the first transistor MPa second transistor MNcoupled between the first end of the first transistor MPand a supply node, and having a control node coupled to a first clock signal node PHI; a third transistor MNcoupled between the second end of the first transistor MPand the supply node; a charge pump having a first output coupled to a control node of the third transistor MNa level shifter having a first output coupled to a second end of the clock bootstrapped capacitor Ca fourth transistor MNcoupled between the supply node and a control node of the first transistor MPand having a control node coupled to a second output of the charge pump; a capacitor coupled between a second output of the level shifter and a control node of the first transistor; and a fifth transistor MNcoupled between the control node of the bootstrapped switch MNand a common node.

Bootstrapping circuit capable of sampling inputs beyond supply voltage

An analog-to-digital converter device capable of measuring inputs beyond a supply voltage including: an N bit analog-to-digital converter powered by a supply voltage and a reference voltage; a range resolution stage capable of receiving inputs at higher voltages than the supply voltage, providing an input to the analog-to-digital converter, and outputting a logic value of one for the N+1th bit in response to an input signal higher than the reference voltage; and a bootstrapped input multiplexer stage for connecting low voltage input signals directly to the analog-to-digital converter and for connecting input signals that can exceed the supply voltage to the range resolution stage.

Analog-to-digital converter with input signal range greater than supply voltage and extended dynamic range

One embodiment of the present invention may include a programmable gain amplifier comprising an input multiplexer operative to sequentially select input signals for amplification. The input signals may be chosen from a plurality of input signals based on a selection signal. The programmable gain amplifier may include at least one amplifier gain stage operative to apply a variable gain amount to a selected input signal. The programmable gain amplifier may further include a gain mapping component that controls the variable gain amount for each of the selected input signals.

Programmable gain amplifier and method

The low AC impedance input stage circuit for fast startup applications includes: a first transistor coupled between a first input node and a first output node; a second transistor coupled between a second input node and a second output node, and having a control node coupled to a control node of the first transistor; a third transistor coupled to the first input node and having a control node coupled to the control node of the first transistor; a fourth transistor coupled to the second input node and having a control node coupled to the control node of the third transistor; a first blocking device coupled between the third transistor and a first current source; a second blocking device coupled between the fourth transistor and the first current source; and a bias device coupled between the first current source and the control node of the first transistor.

Growing community of inventors

Richardson, TX, United States of America

Mohammad A Al-Shyoukh