Qualcomm Incorporated

Mohamed Waleed Allam

Nan Chen

Paul Penzes

Dipti Ranjan Pal

Shih-Hsin Jason Hu

Mohammad Reza Kakoee

Navid Toosizadeh

Xiaohua Kong

Martin Saint-Laurent

Esin Terzioglu

Rajit Chandra

Junmou Zhang

Ryan Michael Coutts

Ali Akbar Merrikh

Sorin Adrian Dobre

Min Chen

Mohammad Ghasemazar

Jose Gilberto Corleto Mena

Jasmin Smaila Ibrahimovic

Yuan-cheng Christopher Pan

Ingyeom Kim

Lingyun Wang

Carlos Auyon

Paul Ivan Penzes

An apparatus and a method to adjust a source voltage based on an operating voltage response are provided. The apparatus includes a circuit configured to change state from a first state to a second state comprising receiving an operating voltage from a power source through a power distribution network. The apparatus further includes a sensor configured to measure an operating voltage response to the circuit changing state to receiving the operating voltage. The apparatus further includes a control circuit configured to adjust a source voltage at the power source based on the operating voltage response measured by the sensor. The method includes changing a state to receiving an operating voltage from a power source through a power distribution network, measuring an operating voltage response to the changing state to receiving the operating voltage, and adjusting the source voltage at the power source based on the measured operating voltage response.

Adjusting source voltage based on operating voltage response

A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.

Temporal temperature sensor position offset error correction

A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.

Circuits and methods providing voltage adjustment as processor cores become active based on an observed number of ring oscillator clock ticks

Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.

Power distribution network (PDN) droop/overshoot mitigation in dynamic frequency scaling

An SoC integrated circuit package is provided in which the analog components of a SerDes for an SoC die in the SoC integrated circuit package are segregated into a SerDes interface die in the SoC integrated circuit package.

Split chip solution for die-to-die serdes

Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

Dynamic clock and voltage scaling with low-latency switching

Techniques for estimating state-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining a circuit state for a circuit comprises determining a capacitance of the circuit for each one of a plurality of circuit states, and selecting one of the circuit states based on the determined capacitances.

State-dependent capacitance estimation

An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.

Integrated circuit adaptive voltage scaling with de-aging

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San Diego, CA, United States of America

Mohamed Waleed Allam