Xilinx, Inc.

Samsung Display Co., Ltd.

Mohamed N Elzeftawi

Amir Amirkhany

Anup P Jose

Gaurav Malhotra

Ahmed Elkholy

Younghoon Song

Hongtao Zhang

Declan Carey

Kevin Geary

Guanghua Shu

A system and method for estimating and using pixel compensation coefficients. In some embodiments, the method includes, during a first time interval: comparing a first pixel current for a pixel of the display with a first reference current, to obtain a first pixel current error signal, the first pixel current error signal being the sign of a difference between the first pixel current and the first reference current; and updating one or more compensation coefficients for the pixel, based on the first pixel current error signal.

Estimation of pixel compensation coefficients by adaptation

A system and method for sensing drive current in a pixel. In some embodiments, the system includes: a first pixel, a second pixel, a differential sensing circuit, a reference current source, and a control circuit. The differential sensing circuit may have a first input, a second input, and an output, the first input being connected to a node at which a reference current generated by the reference current source is subtracted from a first pixel current, the first pixel current including a current generated by the first pixel. The second input may be configured to receive a second pixel current, the second pixel current including a current generated by the second pixel. The output may be configured to produce an output signal based on a difference between a current received at the first input and a current received at the second input.

Fully differential front end for sensing

A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.

Correlated double sampling pixel sensing front end

A method of performing coarse calibration of a voltage-mode (VM) driver having a plurality of driver slices connected in parallel includes setting a control code applied to activated driver slices of the plurality of driver slices to a maximum value to minimize an output resistance of the activated driver slices, activating one driver slice of the plurality of driver slices by applying the control code to the one driver slice, while disabling other driver slices of the plurality of driver slices, measuring an output resistance of the VM driver, determining whether the output resistance of the VM driver is greater than a desired resistance, and in response to determining that the output resistance of the VM driver is greater than a desired resistance activating one more driver slice of the plurality of driver slices.

High resolution voltage-mode driver

This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.

Continuous time linear equalization

An integrated circuit and method for providing a variable gain amplifier are disclosed. One embodiment of the a variable gain amplifier comprises at least one load, a cascode circuit coupled to the load, a folded-gilbert stage, coupled to the cascode circuit, the folded-gilbert stage comprising a main differential pair of transistors and an internal pair of transistors, and a digital to analog converter, coupled to the folded-gilbert stage, for steering currents between the main differential pair of transistors and the internal pair of transistors to change a gain of the variable gain amplifier.

Method and apparatus for providing a variable gain amplifier

A continuous time linear equalizer comprises an input of a first equalizer path configured to receive a first differential input signal; an input of a second equalizer path configured to receive a second differential input signal; a first programmable load capacitor coupled to an output of the first equalizer path; a second programmable load capacitor coupled to an output of the second equalizer path; and a programmable source capacitor coupled between the first equalizer path and the second equalizer path.

Circuit for and method of receiving an input signal

An apparatus relates generally to providing a divided signal output. In such an apparatus, a controller is coupled to receive a reference frequency count and a feedback frequency count to determine a difference therebetween to provide a control setting. A divider is coupled to receive the control setting to provide the divided signal output. The divider includes an adjustable load impedance. The control setting is coupled to adjust the load impedance of the divider to adjust a self-resonance frequency of the divider.

Phase-locked loop with an adjustable output divider

An apparatus relates generally to clock and data recovery. A fractional-N phase-locked loop is for receiving a reference signal, and for providing a proportional signal and an integral signal. A ring oscillator of the fractional-N phase-locked loop is for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal. A data-to-frequency control word converter is for receiving data input and the oscillation signal, and for providing a frequency control word. A fractional-N divider of the fractional-N phase-locked loop is for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop. The phase-frequency detector is for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.

Fractional-N PLL-based CDR with a low-frequency reference

An apparatus relates generally to the generation of an oscillating signal. In this apparatus, a fractional-N generator is for receiving a frequency control word and a reference signal. A multiplying injection-locked oscillator is coupled to the fractional-N generator for receiving a clock signal for outputting an oscillating signal. A frequency tracking loop is coupled to the fractional-N generator for receiving the clock signal, and further coupled to the multiplying injection-locked oscillator for receiving the oscillating signal.

Growing community of inventors

Santa Clara, CA, United States of America

Mohamed N Elzeftawi