Vidatronic, Inc.

Mohamed Mostafa Saber Aboudina

Mohamed Ahmed Mohamed El-Nozahi

Moises Emanuel Robinson

Faisal Abdellatif Elseddeek Ali Hussien

Sameh Ahmed Assem Ibrahim

Sameh Assem Ibrahim

Faisal Abdellatif Elseddeek Hussien

Sameh Ahmed Assem Mostafa Ibrahim

Faisal Abdelatif Elsedeek Hussien

A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.

Circuit and method for load detection using switched capacitors

A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output. The enable circuit further includes a first inverter having a third input connected to the chip enable, a fourth input connected to the first output of the clamp circuit, and a second output; a second inverter having a fifth input connected to the second output of the first inverter, a sixth input connected to the supply, and a third output; a memory element having a seventh input connected to the third output of the second inverter, an eighth input, and a fourth output; and a comparator having a ninth input connected to the chip enable, a tenth input connected to a reference signal, an eleventh input connected to the fourth output of the memory element, and a fifth output connected to the eighth input of the memory element.

Circuit and method for low power chip enable circuitry

An automatically reconfigurable Buck-Boost DC-DC converter having an input supply and an output voltage includes a linear regulator (LDO) for Buck configuration; a switched-capacitor DC-DC converter; a capacitor and switch array, and a gain selector to switch between the linear regulator (LDO) when an output DC level is higher than an input DC level (Buck configuration) and the switched-capacitor DC-DC converter when the output DC level is lower than the input DC level (Boost configuration).

Automatically reconfigurable buck-boost DC-DC converter with shared capacitors

A method to adjust the load transient regulation of a low drop-out (LDO)/load switch linear voltage regulator (LVR) with an n-type pass element having an open loop transfer function, including determining during a load transient event if the gate of the pass&#x2014;element goes lower than a scaled value of the output voltage or a constant voltage level, generating a control signal that controls a current sink block if the gate voltage of the pass element is lower than the output voltage, and enabling a current sink block that is controlled by the control signal and connecting the output of the current sink block to the output of the LVR.

Circuit to improve load transient behavior of voltage regulators and load switches

A low drop-out (LDO)/load switch linear voltage regulator (LVR) circuit having a first input terminal and a first output terminal, includes: a passive network with a second input terminal connected to the first input terminal and a second output terminal; a feedback network with a third input terminal connected to the first output terminal and a third output terminal; a pass element having a fourth input terminal connected to the first input terminal, a fourth output terminal connected to the first output terminal and first control terminal; a combiner having a fifth input connected to the second input, a sixth input connected to the third output and a fifth output connected to the first control terminal.

Power supply rejection for voltage regulators using a passive feed-forward network

An architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture method support optionally determining during a power-up phase and by using a load detection circuit, the estimated load parameters that represents at least one selected from a group consisting of: the load time constant and the load resistor at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output load parameters, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is adjusted based on the estimated load parameters.

LDO and load switch supporting a wide range of load capacitance

A soft-start/soft-stop (SS) controller for a voltage regulator. The SS controller includes a power up/down detector configured to perform at least one selected from a group consisting of detecting a power on condition of the voltage regulator to determine a start-up time period and detecting a power off condition of the voltage regulator to determine a shut-down time period, and a ramped reference voltage signal generator configured to perform at least one selected from a group consisting of increasing a voltage level of a ramped reference voltage signal using a pre-determined ramp-up rate during the start-up time period and decreasing the voltage level of the ramped reference voltage signal using a pre-determined ramp-down rate during the shut-down time period, wherein the ramped reference voltage signal is supplied to the voltage regulator for controlling an output voltage level of the voltage regulator.

Voltage regulators with improved startup, shutdown, and transient behavior

A method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The method includes determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.

Growing community of inventors

Giza, Egypt

Mohamed Mostafa Saber Aboudina