Dft Microsystems, Inc.

Mcgill University

Mohamed M Hafed

Gordon W Roberts

Clarence K L Tam

Sébastien Laberge

Bardia Pishdad

Geoffrey D Duerden

Antonio H Chan

A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently phased clock signals to generate a phase-modulated signal. The phase-selecting signal is designed to contain low- and high-frequency components. The phase-modulated signal is input into a phase filter to filter unwanted high-frequency components. The filtered output of the phase filter is input into a data-transmit serializer to serialize a low-speed parallel word into a high-speed jittered test pattern for input into the transceiver circuitry.

High-speed transceiver tester incorporating jitter injection

Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.

Methods of parametric testing in digital circuits

Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits

A high-speed signal testing system that includes a digital circuitry for providing a pattern tester with oscilloscope functionality at minimal implementation cost. The digital circuitry includes a time-base generator that provides a high-speed repeating time-base signal. The time-base signal, in conjunction with a sub-sampler and an accumulation memory, allows the system to zoom in on, and analyze portions of, one or more bits of interest in a repeating pattern present on the signal under test. Such portions of interest include rising and falling edges and constant high and low bit values.

High-speed signal testing system having oscilloscope functionality

Signal-integrity measurement systems and methods utilizing unique time-base generation techniques for controlling the sampling of one or more signals under test. A time-base generator made in accordance with the present disclosure includes a phase filter and modulation circuitry that generates a rapidly varying phase signal as a function of the output of a sigma-delta modulator. The phase filter filters unwanted high-frequency phase components from the rapidly varying phase signal. The filtered signal is used to clock one or more samplers so as to create sampling instances of the signal(s) under test. The sampling instances are then analyze using any one or more of a variety of techniques suited to the type of signal(s) under test.

Signal integrity measurement systems and methods using a predominantly digital time-base generator

A multi-speed jittered signal generator () that generates a full-speed jittered signal () by scaling a low-speed jittered signal () using a frequency scaler (). The low-speed jittered signal is created by injecting a modulation signal () into a reference signal () using a jitter injector (). Injecting jitter into a low-speed reference signal allows the full-speed jittered signal to be of higher quality than conventional jitter signals created by injecting jitter information into a full-speed reference signal. The multi-speed jittered signal generator may be used as part of a testing system () for testing various circuitry, such as high-speed serializer/deserializer circuitry ().

System and method for generating a jittered test signal

A module (') containing an integrated testing system () that includes one or more measurement engines () tightly coupled with a compute engine (). The one or more measurement engines include at least one stimulus instrument () for exciting circuitry of a device-under-test () with one or more stimulus signals, and at least one measurement instrument () that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry () for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine () providing two-way communications between the integrated testing system automated testing equipment () and/or a dedicated user interface () residing on a host computer ().

System and method for testing integrated circuits

An integrated test core for mixed-signal circuits comprises a periodic waveform generator capable of generating arbitrary band-limited waveforms for excitation purposes and a waveform digitizer for extracting an arbitrary waveform from the test circuit's analog response signal. The digitized response may be tested and measured using DSP techniques. Preferably, the waveform generator and digitizer are synchronously controlled. The core is a nearly all digital implementation with the exception of a reconstruction filter (optional) for sending the test signal to the circuit under test (CUT) and the comparator for extracting the digitized waveform from the CUT's response. The periodic waveform generator may comprise a &#x3a3;&#x394; modulator and, optionally, a reconstruction filter between the modulator and CUT. The waveform digitizer may comprise a programmable reference voltage generator for providing a variable voltage reference signal, a comparator for generating a comparison signal from the CUT's analog response signal and the reference signal and means for controlling the reference voltage generator.

Integrated excitation/extraction system for test and measurement

An efficient technique for generating accurate on-chip DC reference voltages is based on filtering a digital pulse modulated sequence in order to extract its average value encoding a DC level, A passive on-chip filter is used for simplicity with an all-digital modulator implementation. Modulation is proposed using pulse-width and preferably pulse-density modulation methods. The latter has the advantage of using a significantly smaller filter which translates into a smaller implementation and faster operational settling times. Many digital pulse modulation generators are proposed.

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Montreal, Canada

Mohamed M Hafed