Silicon Laboratories Inc.

Shenzhen Goodix Technology Co., Ltd.

Mohamed M Elsayed

Matthew Powell

Chao Yang

Xiaodong Wang

Kenneth Wilson Fernald

Dazhi Wei

Shouli Yan

Scott D Willingham

Praveen Kallam

Nicholas Montgomery Atkinson

Axel Thomsen

Yan Zhou

Scott Willingham

Clayton H Daigle

Sudipta Sarkar

Cheng Zhu

Mohit Kumar

Techniques are described for touch event sensing in a capacitive touch panel that is integrated with a display. In some such environments, a large amount of display noise is capacitively coupled with the touch sensing signals. This can degrade performance of conventional sensing approaches, which tend to use a buffering stage followed by a difference amplifier stage. Embodiments provide a single-stage, differential-difference-amplifier-based touch event sensing approach that pre-cancels coupled display noise from adjacent channels by common-mode rejection prior to amplifying, thereby generating amplified differential output signals that include substantially only the desired touch sensing information.

Differential-difference-amplifier-based touch sensor interface

Techniques are described for using a multi-branch AC-mode bridge approach with global current rotation for self-capacitor sensing in a capacitive touch panel, such as integrated into a display of a touchscreen electronic device. K channels are coupled with K branches of a multi-branch AC-mode bridge to form K−1 pairs of channels for concurrent differential readout. K nominally identical sinusoidal input currents are generated based on an error signal, which is generated based on comparing a sinusoidal driver signal with feedback from one or more of the K branches. A unit current rotator rotates the K sinusoidal input currents to each of the branches, so that each branch current is formed by a rotating contribution from each of the sinusoidal input currents. Driving each branch with its branch current manifests a respective branch voltage, and differences between the branch voltages can be used to differentially sense pairs of channels.

Self-capacitor sensing using alternating-current-mode bridge with global current rotation for capacitive touch panels

Techniques are described for using an alternating-current-mode (AC-mode) bridge for low-noise self-capacitor sensing in a capacitive touch panel array integrated with a display panel. Each channel of the array has a self-capacitance (Ci) that changes responsive to presence or absence of a local touch event local. Pairs of channels are read out differentially by coupling pairs of channels to branches of an AC-mode bridge. The AC-mode bridge includes current sources that drive each branch (and thereby each channel) with a sinusoidal current, manifesting a branch voltage on each branch based on the self-capacitance of the branch. The branch voltages are used to generate an output voltage. The sinusoidal current is controlled by comparing a driver signal with feedback from the branches, so that common-mode noise on the channels becomes a common-mode component of the sinusoidal currents and is rejected in the generation of the output voltage.

Self-capacitor sensing using alternating-current-mode bridge for capacitive touch panels

An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Reduced-leakage apparatus for sampling electrical signals and associated methods

An image sensor includes a plurality of image sensor cells, each configured to generate or not generate an image signal in response to one or more control signals, and a first driver generating a first control signal. The first driver includes a first positive supply terminal connected to a first power supply node. The image sensor also includes a voltage generator generating a first voltage at the first power supply node, where the voltage generator includes a plurality of charge pump cells selectably sourcing charge to the first power supply node in response to one of multiple enable signals, and a charge pump cell quantity controller circuit generating the enable signals. Each enable signal is either in an active or inactive state, and each charge pump cell sources charge to the first power supply node in response to receiving an enable signal in an active state.

Image sensor with charge pump cell quantity control

An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Apparatus with electronic circuitry having reduced leakage current and associated methods

Techniques are described for implementing read-out architectures to support high-speed serialized read-out of a large number of digital bit values, such as for high-resolution pixel conversions in CMOS image sensor applications. For example, outputs from a large number of digital data sources (e.g., counters) are coupled with transmission gates of the read-out architecture, and the transmission gates are sequentially enabled, thereby shifting in bit data from the data sources one at a time. The transmission gates are grouped into gate groups. For each gate group, embodiments seek balance total path delay across the gate groups by controlling clock and data path delays to be inversely related, and ensuring that total path delays for all gate groups are within a single clock period. Some embodiments include a partitioned bus for further gate group-level control over the path delay and data bus capacitance.

Digital serial read-out architecture

Techniques are described for controlling operation of a pixel conversion ADC in a manner that enforces strict timing and synchronization of ramp and clock signaling. Synchronizing techniques can be applied to generate a corrected ramp start signal based on synchronizing a received ramp start signal to an input clocking signal, and to generate a controller clock signal based on synchronizing an input clocking signal to the corrected ramp start signal. The corrected ramp start signal and the controller clock signal can be used to control generation of a ramp enable signal for controlling timing of pixel ramp voltage generation digital pixel conversion counting, and to control generation of an output clocking signal used by the digital pixel conversion counting.

Pixel ramp generator controller for image sensor

Techniques are described for implementing ramp voltage generators with current steering architectures that provide high power supply noise rejection. For example, a current steering architecture uses a sample and hold block and a driver block to control and drive a current steering network. Both generate signals that track supply voltage variations, and those signals are used to generate a ramp voltage. For image sensor applications, image tolerance to ramp noise can be very low when the ramp voltage is low, but can increase appreciably as the ramp voltage increases. As such, embodiments can be implemented to provide high PSR at low ramp voltages, even if the PSR degrades at higher ramp voltages, while maintaining high linearity over the entire ramp voltage.

Current steering architecture with high supply noise rejection

Techniques are described for implementing counter architectures to support high-speed, high-resolution pixel conversions, such as for CMOS image sensor applications. Embodiments implement a counter block that uses loadable true-signal-phase-clocking (L-TSPC) flops for at least a portion of the counter flops. Some embodiments support efficient two-phase pixel conversion by integrating counting, subtraction, and shifting out in the counter. For example, embodiments can perform a first high-speed pixel conversion phase to obtain a first conversion count. Prior to a second phase, the initial counter can be pre-subtracted by the amount of the first conversion count. Embodiments can then perform a second high-speed pixel conversion phase to obtain a second conversion count. As the second conversion count already has the first conversion count pre-subtracted, the second conversion count represents the final two-phase conversion result. Embodiments can read out this final two-phase conversion result as a digital output of the counter.

Loadable true-single-phase-clocking flop-based counter

Techniques are described for implementing reduced-noise pixel ramp voltage generators for image sensors. The described pixel ramp voltage generators include circuit blocks to address various conventional causes of ramp generator noise. For example, a reference current is generated. Current steering can be used to toggle between a ramp-run mode for generation of a ramp voltage, and a ramp-stop mode for stopping the generation, thereby mitigating changes in low-frequency noise components between pixel conversion cycles, or phases or such cycles. Buffer multiplier techniques can be used to isolate kickback noise of the pixel conversion comparators from components generating the ramp voltage, such as to mitigate image smearing. Some implementations include additional features, such as sample-and-hold techniques used to isolate ramp generation components from current generation component noise, slope calibration techniques to dynamically tune voltage ramp slope, reset techniques, etc.

Pixel ramp generator for image sensor

An image sensor includes a pixel array having a plurality of pixels arranged in rows and columns, a plurality of pixel readout lines coupled to respective pixels, a multiplexing circuit coupled to the pixel readout lines, a plurality of analog-to-digital converters coupled to the multiplexing circuit, and a controller configured to provide pixel readout signals of pixels arranged in a same column to the analog-to-digital converters through the multiplexing circuit for concurrent signal conversion.

Using pixel readout reordering to reduce pattern noise in image sensor

An image sensor includes a controller and a plurality of pixel clusters. Each of the pixel clusters includes a plurality of pixels coupled to a reset transistor, a floating diffusion node, a source follower, and a select transistor. Each pixel of a pixel cluster includes a photodiode, and a transfer transistor having a first terminal coupled to the photodiode, a second terminal coupled to the floating diffusion node, and a gate. The controller is configured to apply a transfer control signal to the gate of the transfer transistor in response to a pixel operation, the transfer control signal being one of a positive voltage level, a negative voltage level, and a ground voltage level.

Two level TX low control for simultaneous improved noise and dark current

An image sensor includes a plurality of pixel columns and a plurality of readout circuits. Each readout circuit is coupled to one of the plurality of pixel columns and includes an ADC for receiving a first analog signal of a pixel in a reset conversion phase and a second analog signal of the pixel in a signal measurement phase, a dual-ramp generator for generating a first ramp having a first ramp rate and a second ramp having a second ramp rate greater than the first ramp rate and providing the first ramp to the readout circuits in the reset conversion phase and the second ramp to the plurality of readout circuits in the signal measurement phase, and a controller configured to provide control signals to the readout circuits and the dual-ramp generator.

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Austin, TX, United States of America

Mohamed M Elsayed