Silicon Laboratories Inc.

Mohamed M Elkholy

Mustafa H Koroglu

Ruifeng Sun

Francesco Barale

Essam S Atalla

Steffen Skaug

Navin Harwalkar

Arup Mukherji

Wenhuan Yu

Michael D Mulligan

Hatem M Osman

Anil Shirwaikar

Tiago Pinto Guia Marques

Ayman Shafik

Yang Gao

Ahmed Emira

Håkon Børli

In one embodiment, a method includes: enabling a pulse pair circuit of an integrated circuit in response to determining that a receiver associated with the integrated circuit is active; identifying that at least one comparator of a multi-output DC-DC converter trips, the DC-DC converter having a plurality of comparators each to compare a regulated voltage output by the DC-DC converter to a corresponding reference voltage; and generating, in the pulse pair circuit, a control pulse pair according to the tripped output, and driving a driver circuit of the DC-DC converter using the control pulse pair.

Apparatus, method and system for pulse pairing in a multi-output DC-DC converter

A first three state driver injects a first clock signal into a crystal through an input node during a startup phase of a crystal oscillator and a second three state driver injects a second signal into the crystal through an output node during the startup phase. The first and second signals are anti-phase signals. The crystal oscillator circuit includes a first amplifier that is used during starting up and steady-state operation and includes a second amplifier. The injection through the input and output nodes is disabled after a fixed time. After injection ends, the second amplifier is turned on if voltage on the output node has reached a desired voltage and left off otherwise. If the second amplifier is turned on, the second amplifier is turned off when the voltage on the output node reaches the desired voltage.

Fast startup crystal oscillator circuit with programmable injection time and adaptive startup time to achieve high amplitude oscillation

A frequency synthesizer on an integrated circuit provides a local oscillator (LO) signal for RF operations and also functions as an injection clock signal source during crystal oscillator startup. The integrated circuit goes into a sleep mode in which the crystal oscillator is off and responsive to a wakeup event the crystal oscillator starts up again using the injection clock signal sourced from the frequency synthesizer. Parameters that cause the injection clock signal to match the crystal oscillator frequency are stored. The frequency synthesizer includes a phase-locked loop having an LC oscillator. A digital to analog converter controls the LC oscillator during injection. During an initial power up of the integrated circuit, a PLL in the frequency synthesizer locks to the crystal oscillator frequency to determine the parameters to store for injection.

Utilizing the LC oscillator of a frequency synthesizer as an injection source for crystal oscillator startup

A wireless transceiver circuit with an impedance matching network within an integrated circuit is disclosed. In some embodiments, the impedance matching network utilizes an inductor, having two portions, disposed on two different metal layers of the integrated circuit. The first end of the first portion of the inductor is in communication with an antenna. The second end of the second portion is in communication with a low noise amplifier for receiving signals and a power amplifier for transmitting RF signals. The second end of the first portion is connected to the first end of the second portion using a via. In another embodiment, the two portions are disposed on the same metal layer, wherein one portion is disposed within the other with a gap separating the two portions. These configurations require less space than using two separate inductors and also have a low coupling coefficient.

Low loss impedance matching circuit network having an inductor with a low coupling coefficient

A DC-DC converter including converter circuitry, a voltage detector providing a low voltage signal, and pulse-pairing circuitry. The converter circuitry may be configured according to a buck or a boost configuration switching between a zero and peak current levels. The pulse-pairing circuitry includes a paired pulse generator, a load detector, and a maximum on timing controller. In response to the low voltage signal, the paired pulse generator activates an on signal for a pair of equal duration on pulses separated by a predetermined pulse separation interval. The on time periods are based on an adjustable time value and a peak current indication. The load detector provides a load adjust signal for adjusting the time value based on sampling the low voltage signal and an off time signal at the start of the second pulse. The maximum on timing controller adjusts the adjustable time value based on the load adjust signal.

System and method of automatic calibration to maximize load current support of DC-DC converter operating in pulse-pairing mode

Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.

On-chip harmonic filtering for radio frequency (RF) communications

Embodiments of transceiver circuits disclosed herein include a first amplifier coupled to receive signals from an antenna during a receive (RX) mode of the transceiver circuit, a second amplifier coupled to transmit signals to the antenna during a transmit (TX) mode of the transceiver circuit, and a single impedance matching network coupled to the antenna and directly connected to a shared node to which the first and second amplifiers are directly connected. The single impedance matching network is configured to transform an impedance of the antenna into a resistance at the shared node. A control circuit is coupled to control the impedance transformation of the single impedance matching network, so as to provide a first resistance at the shared node during RX mode and a second resistance at the shared node during TX mode, wherein the second resistance is different from the first resistance.

Transceiver circuit having a single impedance matching network

In one embodiment, a radio receiver includes: a programmable frequency synthesizer to generate a first clock signal; a first frequency divider to divide the first clock signal to generate a master clock signal; a second frequency divider to divide the master clock signal to generate a mixing signal; and a mixer to downconvert a radio frequency (RF) signal to a second frequency signal using the mixing signal. A voltage converter to couple to the radio receiver includes a switch controllable to switchably couple a first voltage to a storage device and a pulse generator to generate at least one pulse pair formed of a first pulse and a second pulse substantially identical to the first pulse, when a second voltage is less than a first threshold voltage, the second pulse separated from the first pulse by a pulse separation interval.

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Austin, TX, United States of America

Mohamed M Elkholy