Efabless Corporation

Efavless Corporation

Mohamed K Kassem

Michael S Wishart

Sherif Eid

Lucio Lanza

Risto Bell

Rajeev Srivastava

Robert Timothy Edwards

Greg P Shaurette

Bertrand Irissou

John M Hughes

Jeffrey DiCorpo

Mohamed A Shalan

Systems and methods for assembling and developing a System-on-a-chip (SoC) by using templates and designer input data are described. One of the methods includes receiving a request for generating a design of the SoC. In response to the request, a template database is accessed to provide templates of a plurality of designs of systems-on-chips (SoCs). Each of the templates is for a technology application. The method includes receiving a selection of one of the templates. The one of the templates represents components of the SoC. The method also includes receiving a configuration file including configuration data input for the components of the SoC. The method includes compiling the configuration file and a definition file for the SoC to generate design files for the SoC.

Systems and methods for assembling and developing an SoC efficiently using templates and designer input data

Systems and methods for generating an integrated circuit (IC) chip design are described. One of the methods includes receiving, on a data sheet, by a server, electrical parameters of a system on chip (SoC) to be designed. The method further includes receiving physical parameters of the SoC on the data sheet, generating a first design of the SoC according to the electrical parameters and the physical parameters, and receiving test parameters for testing the first design. The method further includes testing, via a design verification tool, the first design by applying the test parameters to the first design, receiving a second design of a second SoC, and coupling the second design to the first design to generate a first IC chip design. The method includes arranging the first IC chip design to be included on a shuttle for fabricating a first IC chip.

Systems and methods for obfuscating a circuit design

Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

Methods for engineering integrated circuit design and development

Systems and methods for managing operations for generating a plurality of designs of an integrated circuit chip are described. One of the methods includes receiving a request with a specification of the integrated circuit chip from a requester account, receiving a plurality of requests from a plurality of community member accounts for viewing the specification, and providing access to the specification to the plurality of community member accounts. The method further includes receiving a plurality of instances of the acceptance from the plurality of community member accounts for creating the plurality of designs, providing access to a plurality of resources to the plurality of community member accounts, and receiving a plurality of design files having the plurality of designs from the plurality of community member accounts. The method includes providing access to the plurality of designs to the requester account for approval or disapproval of the plurality of designs.

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

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Carlsbad, CA, United States of America

Mohamed K Kassem