Infineon Technologies Austria Ag

Infineon Technologies Americas Corp.

Mohamed Imam

Hyeongnam Kim

Alain Charles

Bhargav Pandya

Jens Ulrich Heinle

Ramakrishna Tadikonda

Yang Pan

Florin Udrea

Gerhard Prechtl

Kennith Kin Leong

Giorgia Longobardi

Eric G Persson

Mihir Tungare

Gianluca Camuso

Jianwei Wan

Manuel Vorwerk

Chan Kyung Choi

Qin Lei

Chunhui Liu

Shu Yang

Dario Pagnano

Jinming Sun

A Group III nitride transistor cell is provided that includes a Group III nitride-based body, a source finger, a gate finger, and a drain finger extending substantially parallel to one another and positioned on the Group III nitride-based body, the gate finger being arranged laterally between the source finger and the drain finger and including a p-type Group III nitride finger arranged on the Group III nitride body and a gate metal finger arranged on the p-type Group III nitride finger, and a protection diode. The protection diode is integrated into the Group III nitride transistor cell and operable to conduct current in a reverse direction when the Group III nitride transistor cell is switched off. The protection diode is electrically coupled between the source and drain fingers and is positioned on the Group III nitride body laterally between and spaced apart from the gate finger and the drain finger.

Semiconductor device

One or more semiconductor structures comprising a hole draining structure are provided. A semiconductor structure has a first layer formed over a substrate. The first layer has a first concentration of a metal material. The semiconductor structure has a second layer formed over the first layer. The second layer has a second concentration of the metal material different than the first concentration of the metal material. The semiconductor structure has a hole draining structure formed from a superlattice formed between the first layer and the second layer. The hole draining structure has a concentration of the metal material increasing towards the first layer and decreasing towards the second layer.

Hole draining structure for suppression of hole accumulation

The invention relates to a lateral field effect transistor, in particular a HEMT having a heterostructure, in a III/V semiconductor system with a p-type semiconductor being arranged between an ohmic load contact, in particular a drain contact, and a gate contact of the transistor for an injection of holes into a portion of the transistor channel. Further, a recombination zone implemented by a floating ohmic contact is provided for to improve the device performance.

Lateral III/V heterostructure field effect transistor

A transistor package having four terminals includes a semiconductor transistor chip and a semiconductor diode chip. The semiconductor transistor chip includes a control electrode and a first load electrode on a first surface and a second load electrode on a second surface opposite the first surface. The semiconductor diode chip includes a first diode electrode on a first surface and a second diode electrode on a second surface opposite the first surface. The transistor package includes a first terminal electrically connected to the control electrode, a second terminal electrically connected to the first diode electrode, a third terminal electrically connected to the first load electrode and a fourth terminal electrically connected to the second load electrode. At least the first terminal, the second terminal and the third terminal protrude from one side of transistor package. The first terminal is arranged between the second terminal and the third terminal.

Device package having a lateral power transistor with segmented chip pad

A semiconductor device includes type IV semiconductor base substrate, first and second device areas that are electrically isolated from one another, a first region of type III-V semiconductor material formed over the first device area, a second region of type III-V semiconductor material formed over the second device area, the second region of type III-V semiconductor material being laterally electrically insulated from the first region of type III-V semiconductor material, a first high-electron mobility transistor integrally formed in the first region, and a second high-electron mobility transistor integrally formed in the second region. The first and second high-electron mobility transistors are connected in series. A source terminal of the first high-electron mobility transistor is electrically connected to the first device area. The first device area is electrically isolated from a subjacent intrinsically doped region of the base substrate by a first two-way voltage blocking device.

High voltage blocking III-V semiconductor device

A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, and a capacitor monolithically formed in the semiconductor die, wherein a dielectric medium of the capacitor includes a first section of the barrier layer.

Type III-V semiconductor substrate with monolithically integrated capacitor

A semiconductor device includes a main bi-directional switch formed on a semiconductor substrate and having first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain. The semiconductor device further includes a discharge circuit having a plurality of individual transistors or an auxiliary bi-directional switch monolithically integrated with the main bi-directional switch and connected in a common source configuration to the semiconductor substrate. The plurality of individual transistors or the auxiliary bi-directional switch includes a first drain connected to the first source of the main bi-directional switch, a second drain connected to the second source of the main bi-directional switch, and first and second gates each decoupled from gate drive circuitry so that the first and the second gates are controlled at least passively and based on a state of the main bi-directional switch.

Semiconductor device having a bidirectional switch and discharge circuit

A semiconductor device includes a type IV semiconductor base substrate, a first type III-V semiconductor layer formed on a first surface of the base substrate, and a second type III-V semiconductor layer with a different bandgap as the first type III-V being formed on the first type III-V semiconductor layer. The semiconductor device further includes first and second electrically conductive device terminals each being formed on the second type III-V semiconductor layer and each being in ohmic contact with the two-dimensional charge carrier gas. The base substrate includes a first highly doped island that is disposed directly beneath the second device terminal and extends to the first surface of the base substrate. The first highly-doped island is laterally disposed between portions of semiconductor material having a lower net doping concentration than the first highly-doped island.

In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300 V.

Switching circuit, gate driver and method of operating a transistor device

A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, a high-electron mobility transistor disposed in a first lateral region of the semiconductor die, the high-electron mobility transistor comprising source and drain electrodes that each are in ohmic contact with the two-dimensional charge carrier gas and a gate structure that is configured to control a conductive connection between the source and drain electrodes, and a capacitor that is monolithically integrated into the semiconductor die and is disposed in a second lateral region of the semiconductor die, a dielectric medium of the capacitor includes a first section of the barrier layer.

There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron mobility transistor (HEMT) including a III-Nitride intermediate body situated over a substrate, a channel layer situated over the III-Nitride intermediate body, and a barrier layer situated over the channel layer. The channel layer and the barrier layer are configured to produce a two-dimensional electron gas (2DEG). In addition, the III-Nitride transistor includes a dielectric layer situated over the barrier layer, a gate coupled to the barrier layer, and a drain electrode and a source electrode each extending through the dielectric layer. The drain electrode makes ohmic contact with one or both of the barrier layer and a charge trapping prevention layer situated between the dielectric layer and the barrier layer.

Charge trapping prevention III-Nitride transistor

There are disclosed herein various implementations of a group III-V composite transistor having a switched substrate. Such a group III-V composite transistor includes a composite field-effect transistor (FET) including a depletion mode group III-V high electron mobility transistor (HEMT) situated over a substrate. The depletion mode group III-V HEMT is cascoded with an enhancement mode group IV FET to produce the composite FET. The group III-V composite transistor also includes a transistor configured to selectably couple the substrate of the depletion mode group III-V HEMT to ground and to selectably decouple the substrate from ground. That transistor is configured to ground the substrate when the depletion mode group III-V HEMT is in an off-state and to cause the substrate to float when the depletion mode group III-V HEMT is in an on-state.

Composite group III-V and group IV transistor having a switched substrate

There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a selectably floating substrate. Such a group III-V HEMT is situated over a substrate, and includes a transistor configured to selectably couple the substrate to ground and to selectably decouple the substrate from ground. The transistor is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state.

Growing community of inventors

Chandler, AZ, United States of America

Mohamed Imam