Semiconductor Components Industries, LLC

Other

Mohamed Imam

Zia Hossain

Joe Fulton

Jefferson W Hall

Mohammed Tanvir Quddus

Evgueniy Nikolov Stefanov

Takeshi Ishiguro

Raj Nair

Taku Yamamoto

Yoshio Enosawa

Katsuya Yamazaki

Masami Tanaka

Rajesh S Nair

Masaru Suzuki

Charles Hoggatt

A structure for making a LDMOS transistor () includes an interdigitated source finger () and a drain finger () on a substrate (). Termination regions () are formed at the tips of the source finger and drain finger. A drain () of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region () of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

LDMOS transistor with enhanced termination region for high breakdown voltage with on-resistance

LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance

A transistor () is formed to have a body contact () that has a minimal contact to the sides of the source region (). This increases the density and reduces on-resistance of the transistor ().

Method of forming a body contact of a transistor and structure therefor

A high voltage MOSFET device ( ) has an nwell region ( ) with a p-top layer ( ) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability

A method of forming a semiconductor device ( ) forms a plurality of P and N stripes ( ) within a first region ( ) that is formed with an opposite conductivity to a substrate ( ). The plurality of P and N stripes assist in providing a low on-resistance. A portion ( ) of the first region underlies the P and N stripes and protects the semiconductor device from high voltages applied to the drain. A base layer ( ) and a cap layer ( ) further reduce the on-resistance of the semiconductor device.

Method of forming a semiconductor device and structure therefor

A semiconductor device ( ) is disclosed which can accommodate a negative voltage on its source using a P-type substrate ( ) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region ( ) is recessed by a dimension (X) from a first insulated region ( ). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure ( ) having a shape which surrounds a drain contact region ( ) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region ( ) is formed in a P-type region ( ) centered inside the gate structure ( ).

NMOSFET with negative voltage capability formed in P-type substrate and method of making the same

A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion and merge together into a single channel region. The resulting channel region has a dopant concentration that is less than the dopant concentrations of the individual HV regions. The compact MOS device exhibits a low threshold voltage characteristic.

Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same

A semiconductor device ( ) is formed on a substrate ( ) that has first and second well regions ( ) formed at a surface ( ) of the substrate. A control electrode ( ) extends over the surface to activate a first channel ( ) with a control signal (V ) for routing a current (I ) from a first node ( ) of the semiconductor device to an edge ( ) of the first well region. The control signal further activates a second channel ( ) for routing the current from an edge ( ) of the second well region to a second node ( ) of the semiconductor device.

Merged semiconductor device and method

A high voltage MOSFET device ( ) has a well region ( ) with two areas. The first area ( ) has a high dopant concentration and the second area ( ) has a low dopant concentration. Inside the well region a region of a secondary conductivity type ( ) is formed. The second area ( ) is typically underlying a gate region ( ). The lower doping concentration in that area helps to increase the breakdown voltage when the semiconductor device is blocking voltage and helps to decrease the on-resistance when the semiconductor device is in the &ldquo;on&rdquo; state. The MOSFET device further has a p-top layer ( ) which is disposed on the top surface of the well region and then driven into the well region by annealing the MOSFET device at a high temperature in an inert atmosphere.

Method for manufacturing a high voltage MOSFET device with reduced on-resistance

A high voltage MOS device ( ) is disclosed. The MOS device comprises an n-well region ( ) with two areas. The first area ( ) has a high dopant concentration and the second area ( ) has a low dopant concentration. Inside the well region a region of a secondary conductivity type ( ) is formed. The second area ( ) is typically underlying a gate ( ). The lower doping concentration in that area helps to increase the breakdown voltage when the device is blocking voltage and helps to decrease on-resistance when the device is in the &ldquo;on&rdquo; state.

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Tempe, AZ, United States of America

Mohamed Imam