Shenzhen Goodix Technology Co., Ltd.

Goodix Technology Inc.

Mohamed Aboudina

Ahmed Emira

Hassan Osama Elwan

Ali Farid

Faisal Hussien

Esmail Babakrpur Nalousi

Ayman Mohamed Elsayed

Mostafa Elmala

Janakan Sivasubramaniam

Amr Abuellil

Mohamed Yehya Abbas Abdelgawad Nada

Techniques are described herein for phase modulation and interpolation that support high phase modulation resolution with high linearity. Embodiments receive a digital signal that uses a sequence of K-bit digital codes to encode a sequence of instantaneous phases for phase-modulating a local oscillator signal. A fractional divider divides a reference clock into N divided clock signals at equally spaced phase intervals and selects a pair of such signals based on first designated bits of the digital code. A fractional divider-calibrated delay line generates M delayed clock signals at equally spaced phase intervals between the selected pair of divided clock signals, and selects a pair of the delayed clock signals based on second designated bits of the digital code. A digital controlled edge interpolator generates a delayed local oscillator output signal by interpolating between the selected pair of delayed clock signals based on third designated bits of the digital code.

Fractional divider-calibrated phase modulator and interpolator for a wireless transmitter

A communication circuit is disclosed. The communication circuit includes a calibration system, configured to receive clock signals respectively having first and second clock phases, and first and second duty cycles, where the calibration system is further configured to receive input data and to adjust the input data to generate adjusted data based partly on the input data and based partly on the first and second duty cycles. The communication circuit also includes a mixer, configured to receive the clock signals and to receive the adjusted data, where the mixer is configured to generate output data based on the clock signals and the adjusted data, and where a mismatch in the output data caused by the first and second duty cycles being different is reduced because of the adjustment made to the input data to generate the adjusted data.

IQ clock phase calibration

A communication circuit is disclosed. The communication circuit includes a clock input, and a clock divider configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor of (2N+1)/2N, where the clock divider is configured to generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal, generate 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, where the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and generate the output clock signal based at least in part on the 2N unique phase shifted clock signals, and a mixer, configured to receive the output clock signal.

Fractional clock divider

A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.

Receiver circuits with blocker attenuating rf filter

A radio frequency (RF) receiver circuit is disclosed. The RF receiver circuit includes a variable gain amplifier, configured to receive an input RF signal, and to generate an amplified RF signal based on the input RF signal, where a gain of the variable gain amplifier is variable. The RF receiver circuit also includes an RF level indicator circuit, configured to sample the amplified RF signal at non-periodic sampling intervals to generate a plurality of sampled RF signals, and to compare the sampled RF signals with one or more thresholds to generate a plurality of comparison result signals. The gain of the variable gain amplifier is determined based at least in part on the comparison result signals.

Radio frequency level indicator

An electronic system is disclosed. The system has a differential signal generator configured to generate first and second single ended signals having opposite polarities. The input signal, and the first and second single ended signals transition between a first power voltage and a first ground voltage. The system also has a glitch management circuit configured to generate an output signal based on the first and second single ended signals, where the output signal transitions between a second power voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single ended signals, and to generate first and second intermediate signals. The first and second intermediate signals each transition between the second power voltage and the second ground voltage. The system also has a second latch configured generate the output signal based on the first and second intermediate signals.

Deglitch circuit

A receiver circuit includes a mixer receiving an RF signal encoding an information signal. The mixer receives a number of multiphase oscillator signals and generates multiphase baseband signals. The receiver circuit also includes a variable gain circuit receives the multiphase baseband signals, generates a first output signal having a first distortion, and a second output signal having a second distortion. The variable gain circuit is configured to generate a reduced distortion output signal based on the first and second output signals.

Harmonic rejection in multiphase signals

An amplifier circuit is disclosed. The amplifier circuit includes an input terminal configured to receive an input signal, an output terminal configured to transmit an output signal, and a first signal path including a first amplifying circuit, where the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and where the first amplified output includes first amplifier circuit harmonic noise. The amplifier circuit also includes a second signal path including a second amplifying circuit, where the second amplifying circuit receives the input signal and transmits a second amplified output to the output terminal, and where the second amplified output includes second amplifier circuit harmonic noise. The output signal includes the first and second amplified outputs, and the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.

High linearity low noise amplifier

A receiver circuit is disclosed. The receiver circuit includes an amplifier having an input terminal, where the amplifier is configured to generate an RF signal based on a signal received at the input terminal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes a mixer configured to receive the RF signal and to downconvert the RF signal to generate a baseband signal, where the baseband signal includes the information signal and the blocker signal modulating a baseband carrier frequency, where the baseband carrier frequency is less than the RF carrier frequency, and where the mixer is further configured to selectively attenuate the blocker signal.

Receiver circuits with blocker attenuating mixer

An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

Successive approximation register (SAR) analog to digital converter (ADC) with overlapping reference voltage ranges

Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.

Fast wakeup for crystal oscillator

A semiconductor device includes a current source, an input/output (IO) region having a first IO device and a second IO device, and a core region having a core device. The first and second IO devices form with the current source a current mirror circuit. Each of the first and second IO devices has a first threshold voltage, and the core device has a second threshold voltage that is lower than the first threshold voltage. The first core device is coupled to the first and second IO devices and the current source and provides an offset voltage to the current source.

Low-voltage reference current circuit

Receiver circuits with blocker attenuating RF filter

A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.

Growing community of inventors

San Diego, CA, United States of America

Mohamed Aboudina