Intel Corporation

Analog Devices International Unlimited Company

Other

Mohamed Abdelsalam

Nasser A Kurd

Mohamed A Abdelmoneum

Amr M Lotfy

Mohammed W El Mahalawy

Mamdouh O Abd El-Mejeed

Mark L Elzinga

Ahmed Khalil

Young Min Park

Jagannadha Rao Rapeta

Stuart John McCracken

Mohamed El-Nozahi

Surya Musunuri

Mohamed A Abdalla

Hesham Beshary

Aspects of this disclosure relate to an array calibration system and method using probes disposed between antenna elements. In certain embodiments, the calibration is performed by measuring near-field relative phase and amplitude measurements of the antenna elements and using such relative measurements to adjust the amplitude and phase of the transceivers connected to the antenna elements. In some embodiments, each antenna element within a set of antenna elements transmits a signal that is received by a single probe, and the received signals are assessed to determine relative phase or amplitude measurements. In some embodiments, a single probe transmits a signal that is received by each antenna element within a set of antenna elements, and the received signals are assessed to determine relative phase and amplitude measurements.

Antenna array calibration systems and methods

Systems and methods for multi-chip programming for phased arrays are provided herein. In certain embodiments, a semiconductor device includes one or more inputs configured to receive frame data, an internal memory configured to store the received frame data, and a shift register configured to receive the frame data and comprising a plurality of shift register bit positions. The device further includes a latch configured to store a command type, a first multiplexor configured to select at least one first bit from the shift register based on the command type and provide the at least one first bit to the latch, an output configured to output the frame data, and a second multiplexor configured to select at least one second bit from the shift register based on the command type and provide the at least one second bit to the output.

Multi-chip programming for phased array

Polyphase filters (PPFs) can be used to generate quadrature or other phase-shifted representations of an input signal provided to the PPF. In one approach, a 'passive' polyphase filter can include a combination of resistive and capacitive elements. Such a topology can be referred to as an RC-PPF topology. Another passive circuit topology can be used to provide a PPF, by replacing the resistive elements with inductive elements, and by replacing the capacitive elements with resistive elements. A filter circuit can include cascaded RC-PPF and LR-PPF sections, such as in an alternating manner (e.g., an 'RC-LR' topology). In this approach, a total insertion loss of cascaded LR-PPF and RC-PPF sections can be reduced as compared to using LR-PPF or RC-PPF sections, alone.

Polyphase filter (PPF) including RC-LR sections

Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.

Apparatus and system for digitally controlled oscillator

Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.

Apparatus for dynamically adapting a clock generator with respect to changes in power supply

Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Apparatus and method for fast phase locking for digital phase locked loop

Growing community of inventors

Giza, Egypt

Mohamed Abdelsalam