Intel Corporation

Other

Surfasense LLC

Mohamed A Abdelmoneum

Nasser A Kurd

Rashed Mahameed

Mohamed Abdelsalam

Amr M Lotfy

Gregory F Taylor

Jason A Mix

David E Duarte

Thripthi Hegde

Mamdouh O Abd El-Mejeed

Mohammed W El Mahalawy

Kristen L Dorsey

Narayan Srinivasa

Tanay Karnik

Alexander W Min

Paul J Gwin

Mark E Sprenger

Mark Charles Carbone

Tarek A Ibrahim

Hao-Han Hsu

Andrew W Yeoh

Dong-Ho Han

Kevin Fischer

Tawfik M Rahal-Arabi

Brent R Carlton

Kyungtae Han

Mark L Elzinga

Whitney Michael Bryks

Srinivas Venkata Ramanuja Pietambaram

Eduardo Alban

Peter Sagazio

Catharina Biber

Young Min Park

Yong-Joon Park

Timo Huusari

Jagannadha Rao Rapeta

Gerrit John Vreman

Surya Musunuri

DongHo Hong

Mondira D Pant

David A Kaysen

Sarah Shahraini

Satoshi Suzuki

Joshua Linden Levy

Mamdouh O M M Abdelmejeed

Mamdouh O Abdelmejeed

Stephen Pisenti

Kevin J Fischer

An electronic device and associated methods are disclosed. In one example, the electronic device includes a MEMS die located within a substrate, and below a processor die. In selected examples, the MEMS die includes a resonator. Example methods of forming MEMS resonator devices are also shown.

Integrated MEMS resonator and method

A clock buffer or driver is gated pending reception of verifiable crypto keys. These clock buffer or divers remain gated, thus disabling a processor from any meaningful function, till crypto keys are decoded, verified, and applied to the clock buffer or driver. A low frequency pseudorandom frequency hopping time sequence is generated and used for randomizing spread-spectrum to modulate a reference clock (or output clock) of a frequency synthesizer. This hopping time sequence holds the key to unlocking the crypto keys. The PWM modulated crypto keys are carried by the hopping time sequence. To decode the PWM modulated crypto keys, the hopping time sequence is used. The reference clock which is modulated with crypto keys in the spread-spectrum is sent to a decoder (in a processor) along with the hopping time sequence. The crypto keys are decoded and then used to un-gate the clock buffer.

Intellectual property security locking apparatus and method

Techniques and mechanisms for regulating a temperature of a resonator structure. In an embodiment, a thermoelectric cooler (TEC) is thermally coupled to a resonator which is proximate thereto. The resonator supports operation with an oscillator circuit, wherein a resonance characteristic of the resonator contributes to oscillations of a master clock signal, or other oscillatory signal, which is provided with the oscillator circuit. The TEC provides Peltier functionality to selectively perform either one of heating or cooling the resonator. In another embodiment, the TEC is configured to conduct heat which is transferred via a path between the TEC and the resonator, wherein the path omits any circuitry which is to perform operations which are synchronized based on the oscillatory signal.

Device, system, and method to regulate temperature of a resonator structure

An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.

Clock glitch mitigation apparatus and method

Aspects of the embodiments are directed to systems and devices that include a piezo-electric element comprising a top-side electrode and a bottom-side electrode; a metal contact pad electrically connected to the bottom-side electrode; an electrode electrically connected to the top-side electrode; and an encasement encasing the piezo-electric element. The piezo-electric element can be prepared to include steps and metallization for use in one or more types of packaging.

Packaging for ultrasonic transducers

A method of imaging infrared light is provided which comprises: exciting ultrasonic waves in a metal pillar (e.g., Cu pillar); measuring the Time-of-Flight (ToF) of the ultrasonic wave in the waveguide; whereas the ToF is a function of incident Infrared light energy on the waveguide, and reporting the infrared light energy to capture an image. An apparatus of imaging infrared light is provided which comprises: a transducer; a waveguide coupled with the transducer; and a pixel electronic circuit coupled to the transducer, wherein the transducer includes one or more of: PZT, LiNb, AlN, or GaN.

Infrared imaging apparatus and method

Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.

Apparatus and system for digitally controlled oscillator

Embodiments of the present disclosure provide self-calibrated thermal sensors of an integrated circuit (IC) die and associated techniques and configurations. In one embodiment, a self-calibrating thermal sensing device includes a resonator configured to oscillate at a frequency corresponding with a temperature of circuitry of an integrated circuit (IC) die, wherein the resonator is thermally coupled with the circuitry and configured to operate in a first mode and a second mode and logic operatively coupled with the resonator, and configured to calculate a first temperature corresponding with a first frequency of the resonator in the first mode using a first equation, calculate a second temperature corresponding with a second frequency of the resonator in the second mode using a second equation, and add an offset to the first equation and the second equation based on a result of a comparison of the first temperature and the second temperature. Other embodiments may be described and/or claimed.

Self-calibrated thermal sensors of an integrated circuit die

Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.

Apparatus for dynamically adapting a clock generator with respect to changes in power supply

An embodiment includes an ultrasonic sensor system comprising: a backend material stack including a first metal layer between a substrate and a second metal layer with each of the first and second metal layers including a dielectric material; a ultrasonic sensor including a chamber, having a negative air pressure, that is sealed by first and second electrodes coupled to each other with first and second sidewalls; an interconnect, not included in the sensor, in the second metal layer; wherein (a) a first vertical axis intersects the substrate, the chamber, and the first and second electrodes, (b) a second vertical axis intersects the interconnect and the substrate, (c) a first horizontal axis intersects the chamber, the interconnect, and the first and second sidewalls, and (d) the first and second electrodes and the first and second sidewalls each include copper and each are included in the second metal layer.

Biometric cryptography using micromachined ultrasound transducers

Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Apparatus and method for fast phase locking for digital phase locked loop

Methods and systems may provide for detecting a location of an adjacent ultrasonic receiver of a battery powered device relative to a charging surface of a contactless charger. The charging surface may include an ultrasonic array of transmitter sub arrays, wherein one or more of the transmitter sub arrays may be selectively activated based on the location to focus an ultrasonic beam on the adjacent ultrasonic receiver. In one example, a movement of the adjacent ultrasonic receiver may be detected and the focus of the ultrasonic beam is adjusted in response to the movement.

Ultrasonic universal wireless charging

A MEMS device, such as an accelerometer or gyroscope, fabricated in interconnect metallization compatible with a CMOS microelectronic device. In embodiments, a proof mass has a first body region utilizing a thick metal layer that is separated from a thin metal layer. The thick metal layer has a film thickness that is significantly greater than that of the thin metal layer for increased mass. The proof mass further includes a first sensing structure comprising the thin metal layer, but lacking the thick metal layer for small feature sizes and increased capacitive coupling to a surrounding frame that includes a second sensing structure comprising the thin metal layer, but also lacking the thick metal layer. In further embodiments, the frame is released and includes regions with the thick metal layer to better match film stress-induced static deflection of the proof mass.

MEMS devices utilizing a thick metal layer of an interconnect metal film stack

Growing community of inventors

Portland, OR, United States of America

Mohamed A Abdelmoneum